240 lines
6.4 KiB
C
240 lines
6.4 KiB
C
/*
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* Copyright (c) 2022 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file I2C driver for AndesTech atciic100 IP
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*/
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <soc.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/sys/sys_io.h>
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#define I2C_MAX_COUNT 256
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#define BURST_CMD_COUNT 1
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#define RED_IDR 0x00
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#define REG_CFG 0x10
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#define REG_INTE 0x14
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#define REG_STAT 0x18
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#define REG_ADDR 0x1C
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#define REG_DATA 0x20
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#define REG_CTRL 0x24
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#define REG_CMD 0x28
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#define REG_SET 0x2C
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#define I2C_BASE(dev) \
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((const struct i2c_atciic100_config * const)(dev)->config)->base
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#define I2C_CFG(dev) (I2C_BASE(dev) + REG_CFG)
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#define I2C_INTE(dev) (I2C_BASE(dev) + REG_INTE)
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#define I2C_STAT(dev) (I2C_BASE(dev) + REG_STAT)
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#define I2C_ADDR(dev) (I2C_BASE(dev) + REG_ADDR)
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#define I2C_CMD(dev) (I2C_BASE(dev) + REG_CMD)
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#define I2C_SET(dev) (I2C_BASE(dev) + REG_SET)
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#define I2C_DATA(dev) (I2C_BASE(dev) + REG_DATA)
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#define I2C_CTRL(dev) (I2C_BASE(dev) + REG_CTRL)
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#define TARGET_ADDR_MSK BIT_MASK(10)
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#define DATA_MSK BIT_MASK(8)
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/* Interrupt Enable Register(RW) */
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#define IEN_ALL BIT_MASK(10)
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#define IEN_CMPL BIT(9)
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#define IEN_BYTE_RECV BIT(8)
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#define IEN_BYTE_TRANS BIT(7)
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#define IEN_START BIT(6)
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#define IEN_STOP BIT(5)
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#define IEN_ARB_LOSE BIT(4)
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#define IEN_ADDR_HIT BIT(3)
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#define IEN_FIFO_HALF BIT(2)
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#define IEN_FIFO_FULL BIT(1)
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#define IEN_FIFO_EMPTY BIT(0)
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/* Status Register(RW) */
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#define STATUS_W1C_ALL (BIT_MASK(7) << 3)
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#define STATUS_LINE_SDA BIT(14)
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#define STATUS_LINE_SCL BIT(13)
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#define STATUS_GEN_CALL BIT(12)
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#define STATUS_BUS_BUSY BIT(11)
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#define STATUS_ACK BIT(10)
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#define STATUS_CMPL BIT(9)
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#define STATUS_BYTE_RECV BIT(8)
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#define STATUS_BYTE_TRANS BIT(7)
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#define STATUS_START BIT(6)
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#define STATUS_STOP BIT(5)
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#define STATUS_ARB_LOSE BIT(4)
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#define STATUS_ADDR_HIT BIT(3)
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#define STATUS_FIFO_HALF BIT(2)
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#define STATUS_FIFO_FULL BIT(1)
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#define STATUS_FIFO_EMPTY BIT(0)
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/* Control Register(RW) */
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#define CTRL_PHASE_START BIT(12)
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#define CTRL_PHASE_ADDR BIT(11)
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#define CTRL_PHASE_DATA BIT(10)
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#define CTRL_PHASE_STOP BIT(9)
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#define CTRL_DIR BIT(8)
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#define CTRL_DATA_COUNT BIT_MASK(8)
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/* Command Register(RW) */
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#define CMD_MSK BIT_MASK(3)
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#define CMD_NO_ACT (0x0)
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#define CMD_ISSUE_TRANSACTION (0x1)
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#define CMD_ACK (0x2)
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#define CMD_NACK (0x3)
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#define CMD_CLEAR_FIFO (0x4)
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#define CMD_RESET_I2C (0x5)
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/* Setup Register(RW) */
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#define SETUP_T_SUDAT (BIT_MASK(5) << 24)
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#define SETUP_T_SP (BIT_MASK(3) << 21)
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#define SETUP_T_HDDAT (BIT_MASK(5) << 16)
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#define SETUP_T_SCL_RATIO BIT(13)
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#define SETUP_T_SCLHI (BIT_MASK(9) << 4)
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#define SETUP_DMA_EN BIT(3)
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#define SETUP_CONTROLLER BIT(2)
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#define SETUP_ADDRESSING BIT(1)
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#define SETUP_I2C_EN BIT(0)
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#if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 30000000
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#define SETUP_T_SUDAT_STD (0x3)
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#define SETUP_T_SP_STD (0x1)
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#define SETUP_T_HDDAT_STD (5)
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#define SETUP_T_SCL_RATIO_STD (0x0)
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#define SETUP_T_SCLHI_STD (138)
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#define SETUP_T_SUDAT_FAST (0x0)
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#define SETUP_T_SP_FAST (0x1)
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#define SETUP_T_HDDAT_FAST (5)
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#define SETUP_T_SCL_RATIO_FAST (0x1)
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#define SETUP_T_SCLHI_FAST (18)
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#define SETUP_T_SUDAT_FAST_P (0x0)
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#define SETUP_T_SP_FAST_P (0x1)
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#define SETUP_T_HDDAT_FAST_P (0x0)
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#define SETUP_T_SCL_RATIO_FAST_P (0x1)
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#define SETUP_T_SCLHI_FAST_P (6)
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#elif CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 40000000
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#define SETUP_T_SUDAT_STD (0x4)
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#define SETUP_T_SP_STD (0x2)
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#define SETUP_T_HDDAT_STD (0x6)
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#define SETUP_T_SCL_RATIO_STD (0x0)
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#define SETUP_T_SCLHI_STD (182)
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#define SETUP_T_SUDAT_FAST (0x0)
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#define SETUP_T_SP_FAST (0x2)
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#define SETUP_T_HDDAT_FAST (0x6)
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#define SETUP_T_SCL_RATIO_FAST (0x1)
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#define SETUP_T_SCLHI_FAST (23)
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#define SETUP_T_SUDAT_FAST_P (0x0)
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#define SETUP_T_SP_FAST_P (0x2)
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#define SETUP_T_HDDAT_FAST_P (0x0)
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#define SETUP_T_SCL_RATIO_FAST_P (0x1)
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#define SETUP_T_SCLHI_FAST_P (7)
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#else
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#define SETUP_T_SUDAT_STD (0x9)
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#define SETUP_T_SP_STD (0x3)
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#define SETUP_T_HDDAT_STD (12)
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#define SETUP_T_SCL_RATIO_STD (0x0)
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#define SETUP_T_SCLHI_STD (287)
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#define SETUP_T_SUDAT_FAST (0x0)
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#define SETUP_T_SP_FAST (0x3)
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#define SETUP_T_HDDAT_FAST (12)
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#define SETUP_T_SCL_RATIO_FAST (0x1)
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#define SETUP_T_SCLHI_FAST (38)
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#define SETUP_T_SUDAT_FAST_P (0x0)
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#define SETUP_T_SP_FAST_P (0x3)
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#define SETUP_T_HDDAT_FAST_P (0x0)
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#define SETUP_T_SCL_RATIO_FAST_P (0x1)
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#define SETUP_T_SCLHI_FAST_P (13)
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#endif
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#define SETUP_SPEED_MSK (SETUP_T_SUDAT | \
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SETUP_T_SP | \
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SETUP_T_HDDAT | \
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SETUP_T_SCL_RATIO | \
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SETUP_T_SCLHI)
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#define SETUP_SPEED_STD ((SETUP_T_SUDAT_STD << 24) | \
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(SETUP_T_SP_STD << 21) | \
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(SETUP_T_HDDAT_STD << 16) | \
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(SETUP_T_SCL_RATIO_STD << 13) | \
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(SETUP_T_SCLHI_STD << 4))
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#define SETUP_SPEED_FAST ((SETUP_T_SUDAT_FAST << 24) | \
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(SETUP_T_SP_FAST << 21) | \
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(SETUP_T_HDDAT_FAST << 16) | \
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(SETUP_T_SCL_RATIO_FAST << 13) | \
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(SETUP_T_SCLHI_FAST << 4))
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#define SETUP_SPEED_FAST_PLUS ((SETUP_T_SUDAT_FAST_P << 24) | \
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(SETUP_T_SP_FAST_P << 21) | \
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(SETUP_T_HDDAT_FAST_P << 16) | \
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(SETUP_T_SCL_RATIO_FAST_P << 13)| \
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(SETUP_T_SCLHI_FAST_P << 4))
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#define MAX_XFER_SZ (256)
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enum _i2c_ctrl_reg_item_dir {
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I2C_CONTROLLER_TX = 0x0,
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I2C_CONTROLLER_RX = 0x1,
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I2C_TARGET_TX = 0x1,
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I2C_TARGET_RX = 0x0,
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};
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/* I2C driver running state */
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enum _i2c_driver_state {
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I2C_DRV_NONE = 0x0,
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I2C_DRV_INIT = BIT(0),
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I2C_DRV_POWER = BIT(1),
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I2C_DRV_CFG_PARAM = BIT(2),
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I2C_DRV_CONTROLLER_TX = BIT(3),
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I2C_DRV_CONTROLLER_RX = BIT(4),
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I2C_DRV_TARGET_TX = BIT(5),
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I2C_DRV_TARGET_RX = BIT(6),
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I2C_DRV_CONTROLLER_TX_CMPL = BIT(7),
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I2C_DRV_CONTROLLER_RX_CMPL = BIT(8),
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I2C_DRV_TARGET_TX_CMPL = BIT(9),
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I2C_DRV_TARGET_RX_CMPL = BIT(10),
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};
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/* brief I2C Status */
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struct _i2c_status {
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/* /< Mode: 0=Slave, 1=Master */
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uint32_t mode:1;
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uint32_t general_call: 1;
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uint32_t arbitration_lost : 1;
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uint32_t target_ack : 1;
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};
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struct i2c_atciic100_dev_data_t {
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struct k_sem i2c_busy_sem;
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volatile uint32_t driver_state;
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uint8_t *middleware_rx_buf;
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uint8_t *middleware_tx_buf;
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uint32_t fifo_depth;
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uint32_t target_addr;
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uint32_t xfer_wt_num;
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uint32_t xfer_rd_num;
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uint32_t xfered_data_wt_ptr; /* write pointer */
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uint32_t xfered_data_rd_ptr; /* read pointer */
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volatile struct _i2c_status status;
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const struct i2c_target_callbacks *target_callbacks;
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struct i2c_target_config *target_config;
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};
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