180 lines
5.9 KiB
C
180 lines
5.9 KiB
C
/* scp.h - TI LM3S6965 System Control Peripherals interface */
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This module defines the System Control Peripheral Registers for TI LM3S6965
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processor. The registers defined are in region 0x400fe000.
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System Control 0x400fe000
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These modules are not defined:
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Hibernation Module 0x400fc000
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Internal Memory 0x400fd000
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Hibernation Module 0x400fc000
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The registers and bit field names are taken from the 'Stellaris LM3S6965
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Microcontroller DATA SHEET (DS-LM3S6965-12746.2515) revision H' document,
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section 5.4/5.5, pp .184-200.
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*/
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#ifndef _SCP_H_
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#define _SCP_H_
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#include <stdint.h>
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#define _SCP_OSC_SOURCE_MAIN 0
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#define _SCP_OSC_SOURCE_INTERNAL 1
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#define _SCP_OSC_SOURCE_INTERNAL_DIV4 2
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#define _SCP_OSC_SOURCE_INTERNAL_20KHZ 3
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#define _SCP_OSC_SOURCE_EXTERNAL_32KHZ 7 /* Valid with RCC2 only */
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#define _SCP_CRYSTAL_1MHZ_NOPLL 0
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#define _SCP_CRYSTAL_1_8432MHZ_NOPLL 1
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#define _SCP_CRYSTAL_2MHZ_NOPLL 2
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#define _SCP_CRYSTAL_2_4576MHZ_NOPLL 3
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#define _SCP_CRYSTAL_3_579545MHZ 4
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#define _SCP_CRYSTAL_3_6864MHZ 5
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#define _SCP_CRYSTAL_4MHZ 6
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#define _SCP_CRYSTAL_4_0964MHZ 7
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#define _SCP_CRYSTAL_4_9152MHZ 8
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#define _SCP_CRYSTAL_5MHZ 9
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#define _SCP_CRYSTAL_5_12MHZ 10
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#define _SCP_CRYSTAL_6MHZ 11 /* reset value */
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#define _SCP_CRYSTAL_6_144MHZ 12
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#define _SCP_CRYSTAL_7_3728MHZ 13
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#define _SCP_CRYSTAL_8MHZ 14
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#define _SCP_CRYSTAL_8_192MHZ 15
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union __rcc {
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uint32_t value;
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struct {
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uint32_t moscdis : 1 __packed;
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uint32_t ioscdis : 1 __packed;
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uint32_t rsvd__2_3 : 2 __packed;
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uint32_t oscsrc : 2 __packed;
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uint32_t xtal : 4 __packed;
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uint32_t rsvd__10 : 1 __packed;
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uint32_t bypass : 1 __packed;
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uint32_t rsvd__12 : 1 __packed;
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uint32_t pwrdn : 1 __packed;
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uint32_t rsvd__14_16 : 3 __packed;
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uint32_t pwmdiv : 3 __packed; /* 2**(n+1) */
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uint32_t usepwmdiv : 1 __packed;
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uint32_t rsvd__21 : 1 __packed;
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uint32_t usesysdiv : 1 __packed;
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uint32_t sysdiv : 4 __packed;
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uint32_t acg : 1 __packed;
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uint32_t rsvd__28_31 : 4 __packed;
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} bit;
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};
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union __rcc2 {
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uint32_t value;
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struct {
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uint8_t rsvd__0_3 : 4 __packed;
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uint8_t oscsrc2 : 3 __packed;
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uint16_t rsvd__7_10 : 4 __packed;
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uint8_t bypass2 : 1 __packed;
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uint8_t rsvd__12 : 1 __packed;
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uint8_t pwrdn2 : 1 __packed;
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uint16_t rsvd__14_22 : 9 __packed;
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uint16_t sysdiv2 : 6 __packed;
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uint8_t rsvd__29_30 : 2 __packed;
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uint8_t usercc2 : 1 __packed;
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} bit;
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};
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struct __scp {
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uint32_t did0; /* 0x000 RO Device ID*/
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uint32_t did1; /* 0x004 RO Device ID*/
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uint32_t dc0; /* 0x008 RO Device Capabilities */
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uint32_t dc1; /* 0x00c RO Device Capabilities */
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uint32_t dc2; /* 0x010 RO Device Capabilities */
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uint32_t dc3; /* 0x014 RO Device Capabilities */
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uint32_t dc4; /* 0x018 RO Device capabilities */
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uint32_t rsvd__01c_02f[(0x30 - 0x1c) / 4];
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uint32_t pborctl; /* 0x030 RW Brown-Out Reset ConTroL */
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uint32_t ldopctl; /* 0x034 RW LDO Power ConTroL */
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uint32_t rsvd__038_03f[(0x40 - 0x38) / 4];
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uint32_t srcr0; /* 0x040 RW Software Reset Control Register */
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uint32_t srcr1; /* 0x044 RW Software Reset Control Register */
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uint32_t srcr2; /* 0x048 RW Software Reset Control Register */
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uint32_t rsvd__04c_04f;
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uint32_t ris; /* 0x050 RO Raw Interrupt Status */
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uint32_t imc; /* 0x054 RW Interrupt Mask Control */
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uint32_t misc; /* 0x058 RW1C Masked Int. Status & Clear */
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uint32_t resc; /* 0x05C RW RESet Cause */
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struct {
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union __rcc rcc; /* 0x060 RW Run-mode Clock Configuration */
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uint32_t pllcfg; /* 0x064 RW xtal-to-pll translation */
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uint32_t rsvd__068_06f[(0x70 - 0x068) / 4];
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union __rcc2 rcc2; /* 0x070 RW Run-mode Clock Configuration */
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uint32_t rsvd__074_0ff[(0x100 - 0x074) / 4];
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uint32_t rcgc0; /* 0x100 RW Run-mode Clock Gating */
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uint32_t rcgc1; /* 0x104 RW Run-mode Clock Gating */
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uint32_t rcgc2; /* 0x108 RW Run-mode Clock Gating */
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uint32_t rsvd__10c_10f;
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uint32_t scgc0; /* 0x110 RW Sleep-mode Clock Gating */
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uint32_t scgc1; /* 0x114 RW Sleep-mode Clock Gating */
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uint32_t scgc2; /* 0x118 RW Sleep-mode Clock Gating */
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uint32_t rsvd__11c_11f;
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uint32_t dcgc0; /* 0x120 RW Deep sleep mode Clock Gating */
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uint32_t dcgc1; /* 0x124 RW Deep sleep mode Clock Gating */
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uint32_t dcgc2; /* 0x128 RW Deep sleep mode Clock Gating */
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uint32_t rsvd__12c_143[(0x144 - 0x12c) / 4];
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uint32_t
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dslpclkcfg; /* 0x144 RW Deep SLeeP CLocK ConFiGuration
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*/
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} clock;
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};
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extern volatile struct __scp __scp;
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#endif /* _SCP_H_ */
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