139 lines
3.7 KiB
C
139 lines
3.7 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Freescale K20 microprocessor Watch Dog registers
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*
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* This module defines Watch Dog Registers for the K20 Family of microprocessors
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*/
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#ifndef _K20WDOG_H_
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#define _K20WDOG_H_
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#include <stdint.h>
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/* Sequence of writes within 20 bus cycles for action to take effect */
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#define WDOG_REFRESH_1 0xA602
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#define WDOG_REFRESH_2 0xB480
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#define WDOG_UNLOCK_1 0xC520
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#define WDOG_UNLOCK_2 0xD928
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union WDOG_STCTRLH {
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uint16_t value; /* reset= 0x01D3 */
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struct {
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uint8_t wdogen : 1 __packed;
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uint8_t clksrc : 1 __packed;
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uint8_t irqrsten : 1 __packed;
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uint8_t winen : 1 __packed;
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uint8_t allowupdate : 1 __packed;
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uint8_t dbgen : 1 __packed;
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uint8_t stopen : 1 __packed;
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uint8_t waiten : 1 __packed;
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uint8_t res_8_9 : 2 __packed;
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uint8_t testwdog : 1 __packed;
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uint8_t testsel : 1 __packed;
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uint8_t bytesel : 2 __packed;
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uint8_t disestwdog : 1 __packed;
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uint8_t res_15 : 1 __packed;
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} field;
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};
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/* K20 Microntroller WDOG module register structure */
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struct K20_WDOG {
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union WDOG_STCTRLH stctrlh; /* 0x00 */
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uint16_t stctrll; /* 0x02 */
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uint16_t tovalh; /* 0x04 */
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uint16_t tovall; /* 0x06 */
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uint16_t winh; /* 0x08 */
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uint16_t winl; /* 0x0A */
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uint16_t refresh; /* 0x0C */
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uint16_t unlock; /* 0x0E */
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uint16_t tmrouth; /* 0x10 */
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uint16_t tmroutl; /* 0x12 */
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uint16_t rstcnt; /* 0x14 */
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uint16_t presc; /* 0x16 */
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};
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/**/
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/**< Macro to enable all interrupts. */
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#define EnableInterrupts __asm__(" CPSIE i");
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/**< Macro to disable all interrupts. */
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#define DisableInterrupts __asm__(" CPSID i");
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/**/
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/**
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*
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* @brief Watchdog timer unlock routine.
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*
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* This routine will unlock the watchdog timer registers for write access.
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* Writing 0xC520 followed by 0xD928 will unlock the write-once registers
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* in the WDOG so they are writable within the WCT period.
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void wdog_unlock(volatile struct K20_WDOG *wdog_p)
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{
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/*
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* NOTE: DO NOT SINGLE STEP THROUGH THIS FUNCTION!!!
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* There are timing requirements for the execution of the unlock
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* process.
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* Single stepping through the code you will cause the CPU to reset.
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*/
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/*
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* This sequence must execute within 20 clock cycles, so disable
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* interrupts to keep the code atomic and ensure the timing.
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*/
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DisableInterrupts;
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/* Write 2-word unlock sequence to unlock register */
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wdog_p->unlock = (uint16_t)WDOG_UNLOCK_1;
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wdog_p->unlock = (uint16_t)WDOG_UNLOCK_2;
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/* Re-enable interrupts now that we are done */
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EnableInterrupts;
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}
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/**
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*
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* @brief Watchdog timer disable routine
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*
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* This routine will disable the watchdog timer.
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void wdog_disable(volatile struct K20_WDOG *wdog_p)
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{
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union WDOG_STCTRLH_t stctrlh;
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/* First unlock the watchdog so that we can write to registers */
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wdog_unlock(wdog_p);
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/*
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* Writes to control/configuration registers must execute within
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* 256 clock cycles after unlocking, so interrupts may need to be
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* disabled to ensure the timing.
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*/
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stctrlh.value = wdog_p->stctrlh.value;
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stctrlh.field.wdogen = 0;
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wdog_p->stctrlh.value = stctrlh.value;
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}
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#endif /* _K20WDOG_H_ */
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