58 lines
2.0 KiB
Plaintext
58 lines
2.0 KiB
Plaintext
Supported Features
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==================
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In addition to the standard architecture devices (HPET, local and I/O APICs,
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etc.), Zephyr supports the following Apollo Lake-specific SoC devices:
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* HSUART
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* GPIO
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* I2C
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HSUART High-Speed Serial Port Support
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-------------------------------------
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The Apollo Lake UARTs are NS16550-compatible, with "high-speed" capability.
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Baud rates beyond 115.2kbps (up to 3.6864Mbps) are supported, with additional
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configuration. The UARTs are fed a master clock which is fed into a PLL which
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in turn outputs the baud master clock. The PLL is controlled by a per-UART
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32-bit register called ``PRV_CLOCK_PARAMS`` (aka the ``PCP``), the format of
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which is:
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+--------+---------+--------+--------+
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| [31] | [30:16] | [15:1] | [0] |
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+========+=========+========+========+
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| enable | ``m`` | ``n`` | toggle |
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+--------+---------+--------+--------+
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The resulting baud master clock frequency is ``(n/m)`` * master.
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Typically, the master clock is 100MHz, and the firmware by default sets
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the ``PCP`` to ``0x3d090240``, i.e., ``n = 288``, ``m = 15625``, which
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results in the de-facto standard 1.8432MHz master clock and a max baud rate
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of 115.2k. Higher baud rates are enabled by changing the PCP and telling
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Zephyr what the resulting master clock is.
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Use devicetree to set the value of the ``PRV_CLOCK_PARAMS`` register in
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the UART block of interest. Typically a devicetree overlay file would be
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present in the application directory (specific to the board, such as
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``up_squared.overlay`` or ``gpmrb.overlay``), with contents like this:
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.. code-block:: console
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/ {
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soc {
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uart@0 {
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pcp = <0x3d090900>;
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clock-frequency = <7372800>;
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current-speed = <230400>;
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};
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};
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};
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The relevant variables are ``pcp`` (the value to use for ``PRV_CLOCK_PARAMS``),
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and ``clock-frequency`` (the resulting baud master clock). The meaning of
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``current-speed`` is unchanged, and as usual indicates the initial baud rate.
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