53 lines
1.1 KiB
C
53 lines
1.1 KiB
C
/* Copyright(c) 2021 Intel Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include <zephyr/devicetree.h>
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#include <soc_util.h>
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#include <zephyr/cache.h>
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#include <adsp_shim.h>
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#include <adsp_memory.h>
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#include <cpu_init.h>
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#include "manifest.h"
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#define DELAY_COUNT 256
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__imr void hp_sram_init(uint32_t memory_size)
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{
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ARG_UNUSED(memory_size);
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uint32_t hpsram_ebb_quantity = ace_hpsram_get_bank_count();
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uint32_t idx;
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for (idx = 0; idx < hpsram_ebb_quantity; ++idx) {
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HPSRAM_REGS(idx)->HSxPGCTL = 0;
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HPSRAM_REGS(idx)->HSxRMCTL = 1;
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}
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for (idx = 0; idx < hpsram_ebb_quantity; ++idx) {
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while (HPSRAM_REGS(idx)->HSxPGISTS != 0) {
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}
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}
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bbzero((void *)L2_SRAM_BASE, L2_SRAM_SIZE);
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}
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__imr void lp_sram_init(void)
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{
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uint32_t lpsram_ebb_quantity = ace_lpsram_get_bank_count();
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uint32_t idx;
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for (idx = 0; idx < lpsram_ebb_quantity; ++idx) {
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LPSRAM_REGS(idx)->USxPGCTL = 0;
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LPSRAM_REGS(idx)->USxRMCTL = 1;
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}
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for (idx = 0; idx < lpsram_ebb_quantity; ++idx) {
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while (LPSRAM_REGS(idx)->USxPGISTS != 0) {
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}
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}
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bbzero((void *)LP_SRAM_BASE, LP_SRAM_SIZE);
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}
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