129 lines
3.1 KiB
Plaintext
129 lines
3.1 KiB
Plaintext
# Intel CAVS SoC family configuration options
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#
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# Copyright (c) 2020 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_INTEL_ADSP
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select WINSTREAM
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select ARCH_SUPPORTS_COREDUMP
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select CPU_HAS_DCACHE
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bool
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if SOC_FAMILY_INTEL_ADSP
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config SOC_FAMILY
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string
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default "intel_adsp"
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# Select SoC Part No. and configuration options
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source "soc/xtensa/intel_adsp/*/Kconfig.soc"
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DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc
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DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc
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config INTEL_ADSP_IPC
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bool "Driver for the host IPC interrupt delivery"
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default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HOST_IPC)) if !SOF
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default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_IDC)) if !SOF
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help
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Driver for the host IPC interrupt delivery mechanism.
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Currently SOF has its own driver for this hardware.
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config MEMORY_WIN_0_SIZE
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int "Size of memory window 0"
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default 8192
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help
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Size of memory window 0.
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This window is used for firmware status & outbox/uplink mbox.
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config MEMORY_WIN_1_SIZE
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int "Size of memory window 1"
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default 8192
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help
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Size of memory window 1.
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This window is used for inbox/downlink mbox.
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config MEMORY_WIN_2_SIZE
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int "Size of memory window 2"
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default 8192
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help
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Size of memory window 2.
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This window is used for debug.
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config MEMORY_WIN_3_SIZE
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int "Size of memory window 3"
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default 8192
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help
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Size of memory window 3.
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This window is used for trace.
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config ADSP_CLOCK
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bool
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help
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Driver for the CAVS clocks. Allow type of clock (and
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thus frequency) to be chosen.
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config HP_SRAM_RESERVE
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int "Bytes to reserve at start of HP-SRAM"
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default 65536
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help
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Bytes to reserve at the start of HP-SRAM. Zephyr will not
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place any symbols here, though the host windows have
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addresses here. The SOF application also makes direct use
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of this region, so be very careful changing this value.
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config ADSP_TRACE_SIMCALL
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bool "Emit SIMCALL output in addition to window tracing"
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help
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When true, the trace_out layer will also use a SIMCALL
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instruction to emit the passed data to the standard output
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of an enclosing simulator process. All window contents will
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remain identical.
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config ADSP_NEED_POWER_ON_CACHE
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bool
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help
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Need to power cache SRAM banks on.
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config ADSP_INIT_HPSRAM
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bool
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default y
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help
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Need to init HP SRAM.
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config ADSP_POWER_DOWN_HPSRAM
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bool
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default n if ZTEST
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default y
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help
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Switch off HP SRAM during power down.
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config ADSP_DISABLE_L2CACHE_AT_BOOT
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bool
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config ADSP_IMR_CONTEXT_SAVE
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bool "Saves FW context into IMR before core is shut down"
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default n
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help
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When true, FW will store its entire context into IMR before
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entering D3 state. Later this context can be used to FW restore
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when Host power up DSP again.
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config XTENSA_CPU_IDLE_SPIN
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bool "Use busy loop for k_cpu_idle"
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help
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Use a spin loop instead of WAITI for the CPU idle state.
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config XTENSA_WAITI_BUG
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bool "Workaround sequence for WAITI bug on LX6"
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help
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SOF traditionally contains this workaround on its ADSP
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platforms which prefixes a WAITI entry with 128 NOP
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instructions followed by an ISYNC and EXTW.
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endif # SOC_FAMILY_INTEL_ADSP
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