61 lines
1.7 KiB
Plaintext
61 lines
1.7 KiB
Plaintext
#
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# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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# SPDX-License-Identifier: Apache-2.0
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#
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# Device data: comp.
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# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
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#
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choice
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prompt "XC7Zxxx SoC Selection"
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depends on SOC_SERIES_XILINX_XC7ZXXX
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config SOC_XILINX_XC7Z010
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bool "XC7Z010"
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help
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2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
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28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins.
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config SOC_XILINX_XC7Z015
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bool "XC7Z015"
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help
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2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
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74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
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up to 4 transceivers.
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config SOC_XILINX_XC7Z020
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bool "XC7Z020"
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help
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2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
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85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
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config SOC_XILINX_XC7Z030
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bool "XC7Z030"
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help
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2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins,
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up to 4 transceivers.
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config SOC_XILINX_XC7Z035
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bool "XC7Z035"
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help
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2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins,
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up to 16 transceivers.
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config SOC_XILINX_XC7Z045
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bool "XC7Z045"
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help
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2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins,
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up to 16 transceivers.
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config SOC_XILINX_XC7Z100
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bool "XC7Z100"
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help
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2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins,
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up to 16 transceivers.
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endchoice
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