29 lines
774 B
C
29 lines
774 B
C
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2021 ASPEED Technology Inc.
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*/
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#ifndef ZEPHYR_SOC_ARM_ASPEED_AST10X0_SOC_H_
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#define ZEPHYR_SOC_ARM_ASPEED_AST10X0_SOC_H_
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#include <aspeed_util.h>
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#define __VTOR_PRESENT 1U
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#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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#define PHY_SRAM_ADDR 0x80000000UL
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#define TO_PHY_ADDR(addr) (PHY_SRAM_ADDR + (uint32_t)(addr))
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#define TO_VIR_ADDR(addr) ((uint32_t)(addr) - PHY_SRAM_ADDR)
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#define SYS_RESET_LOG_REG1 0x7e6e2074
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#define SYS_RESET_LOG_REG2 0x7e6e2078
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#define HW_STRAP1_SCU500 0x7e6e2500
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#define HW_STRAP2_SCU510 0x7e6e2510
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#define ASPEED_FMC_WDT2_CTRL 0x7e620064
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void aspeed_print_sysrst_info(void);
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#endif /* ZEPHYR_SOC_ARM_ASPEED_AST10X0_SOC_H_*/
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