156 lines
4.0 KiB
C
156 lines
4.0 KiB
C
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2021 ASPEED Technology Inc.
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*/
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <stdint.h>
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#include <string.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/device.h>
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#include <zephyr/cache.h>
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#include <soc.h>
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extern char __bss_nc_start__[];
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extern char __bss_nc_end__[];
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/* SCU registers */
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#define JTAG_PINMUX_REG 0x41c
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/* ASPEED System reset contrl/status register */
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#define SYS_WDT4_SW_RESET BIT(31)
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#define SYS_WDT4_ARM_RESET BIT(30)
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#define SYS_WDT4_FULL_RESET BIT(29)
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#define SYS_WDT4_SOC_RESET BIT(28)
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#define SYS_WDT3_SW_RESET BIT(27)
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#define SYS_WDT3_ARM_RESET BIT(26)
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#define SYS_WDT3_FULL_RESET BIT(25)
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#define SYS_WDT3_SOC_RESET BIT(24)
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#define SYS_WDT2_SW_RESET BIT(23)
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#define SYS_WDT2_ARM_RESET BIT(22)
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#define SYS_WDT2_FULL_RESET BIT(21)
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#define SYS_WDT2_SOC_RESET BIT(20)
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#define SYS_WDT1_SW_RESET BIT(19)
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#define SYS_WDT1_ARM_RESET BIT(18)
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#define SYS_WDT1_FULL_RESET BIT(17)
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#define SYS_WDT1_SOC_RESET BIT(16)
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#define SYS_FLASH_ABR_RESET BIT(2)
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#define SYS_EXT_RESET BIT(1)
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#define SYS_PWR_RESET_FLAG BIT(0)
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#define BIT_WDT_SOC(x) SYS_WDT ## x ## _SOC_RESET
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#define BIT_WDT_FULL(x) SYS_WDT ## x ## _FULL_RESET
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#define BIT_WDT_ARM(x) SYS_WDT ## x ## _ARM_RESET
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#define BIT_WDT_SW(x) SYS_WDT ## x ## _SW_RESET
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#define HANDLE_WDTx_RESET(x, event_log, event_log_reg) \
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if (event_log & (BIT_WDT_SOC(x) | BIT_WDT_FULL(x) | BIT_WDT_ARM(x) | BIT_WDT_SW(x))) { \
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printk("RST: WDT%d ", x); \
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if (event_log & BIT_WDT_SOC(x)) { \
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printk("SOC "); \
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sys_write32(BIT_WDT_SOC(x), event_log_reg); \
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} \
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if (event_log & BIT_WDT_FULL(x)) { \
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printk("FULL "); \
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sys_write32(BIT_WDT_FULL(x), event_log_reg); \
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} \
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if (event_log & BIT_WDT_ARM(x)) { \
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printk("ARM "); \
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sys_write32(BIT_WDT_ARM(x), event_log_reg); \
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} \
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if (event_log & BIT_WDT_SW(x)) { \
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printk("SW "); \
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sys_write32(BIT_WDT_SW(x), event_log_reg); \
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} \
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printk("\n"); \
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} \
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(void)(x)
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/* secure boot header : provide image size to bootROM for SPI boot */
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struct sb_header {
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uint32_t key_location;
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uint32_t enc_img_addr;
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uint32_t img_size;
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uint32_t sign_location;
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uint32_t header_rev[2];
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uint32_t patch_location;
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uint32_t checksum;
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};
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struct sb_header sbh __attribute((used, section(".sboot"))) = {
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.img_size = (uint32_t)&__bss_start,
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};
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void z_arm_platform_init(void)
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{
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uint32_t jtag_pinmux;
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uint32_t base = DT_REG_ADDR(DT_NODELABEL(syscon));
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/* enable JTAG pins */
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jtag_pinmux = sys_read32(base + JTAG_PINMUX_REG);
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jtag_pinmux |= (0x1f << 25);
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sys_write32(jtag_pinmux, base + JTAG_PINMUX_REG);
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/* clear non-cached .bss */
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if (CONFIG_SRAM_NC_SIZE > 0) {
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(void)memset(__bss_nc_start__, 0, __bss_nc_end__ - __bss_nc_start__);
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}
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sys_cache_instr_enable();
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}
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void aspeed_print_abr_wdt_mode(void)
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{
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/* ABR enable */
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if (sys_read32(HW_STRAP2_SCU510) & BIT(11)) {
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printk("FMC ABR: Enable");
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if (sys_read32(HW_STRAP2_SCU510) & BIT(12))
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printk(", Single flash");
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else
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printk(", Dual flashes");
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printk(", Source: %s (%d)",
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(sys_read32(ASPEED_FMC_WDT2_CTRL) & BIT(4)) ? "Alternate" : "Primary",
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(sys_read32(HW_STRAP1_SCU500) & BIT(3)) ? 1 : 0);
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if (sys_read32(HW_STRAP2_SCU510) & GENMASK(15, 13)) {
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printk(", bspi sz: %ldMB",
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BIT((sys_read32(HW_STRAP2_SCU510) >> 13) & 0x7) / 2);
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}
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printk("\n");
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}
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}
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void aspeed_print_sysrst_info(void)
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{
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uint32_t rest1 = sys_read32(SYS_RESET_LOG_REG1);
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uint32_t rest2 = sys_read32(SYS_RESET_LOG_REG2);
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if (rest1 & SYS_PWR_RESET_FLAG) {
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printk("RST: Power On\n");
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sys_write32(rest1, SYS_RESET_LOG_REG1);
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} else {
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HANDLE_WDTx_RESET(4, rest1, SYS_RESET_LOG_REG1);
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HANDLE_WDTx_RESET(3, rest1, SYS_RESET_LOG_REG1);
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HANDLE_WDTx_RESET(2, rest1, SYS_RESET_LOG_REG1);
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HANDLE_WDTx_RESET(1, rest1, SYS_RESET_LOG_REG1);
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if (rest1 & SYS_FLASH_ABR_RESET) {
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printk("RST: SYS_FLASH_ABR_RESET\n");
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sys_write32(SYS_FLASH_ABR_RESET, SYS_RESET_LOG_REG1);
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}
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if (rest1 & SYS_EXT_RESET) {
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printk("RST: External\n");
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sys_write32(SYS_EXT_RESET, SYS_RESET_LOG_REG1);
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}
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}
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ARG_UNUSED(rest2);
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aspeed_print_abr_wdt_mode();
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}
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