173 lines
3.4 KiB
C
173 lines
3.4 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited
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* 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <flash.h>
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#include <string.h>
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static inline bool is_aligned_32(u32_t data)
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{
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return (data & 0x3) ? false : true;
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}
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static inline bool is_addr_valid(off_t addr, size_t len)
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{
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if (addr + len > NRF_FICR->CODEPAGESIZE * NRF_FICR->CODESIZE ||
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addr < 0) {
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return false;
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}
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return true;
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}
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static void nvmc_wait_ready(void)
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{
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
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;
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}
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}
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static int flash_nrf5_read(struct device *dev, off_t addr,
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void *data, size_t len)
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{
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if (!is_addr_valid(addr, len)) {
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return -EINVAL;
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}
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if (!len) {
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return 0;
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}
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memcpy(data, (void *)addr, len);
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return 0;
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}
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static int flash_nrf5_write(struct device *dev, off_t addr,
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const void *data, size_t len)
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{
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u32_t addr_word;
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u32_t tmp_word;
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void *data_word;
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u32_t remaining = len;
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u32_t count = 0;
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if (!is_addr_valid(addr, len)) {
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return -EINVAL;
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}
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if (!len) {
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return 0;
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}
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/* Start with a word-aligned address and handle the offset */
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addr_word = addr & ~0x3;
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/* If not aligned, read first word, update and write it back */
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if (!is_aligned_32(addr)) {
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tmp_word = *(u32_t *)(addr_word);
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count = sizeof(u32_t) - (addr & 0x3);
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if (count > len) {
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count = len;
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}
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memcpy((u8_t *)&tmp_word + (addr & 0x3), data, count);
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nvmc_wait_ready();
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*(u32_t *)addr_word = tmp_word;
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addr_word = addr + count;
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remaining -= count;
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}
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/* Write all the 4-byte aligned data */
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data_word = (void *) data + count;
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while (remaining >= sizeof(u32_t)) {
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nvmc_wait_ready();
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*(u32_t *)addr_word = *(u32_t *)data_word;
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addr_word += sizeof(u32_t);
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data_word += sizeof(u32_t);
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remaining -= sizeof(u32_t);
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}
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/* Write remaining data */
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if (remaining) {
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tmp_word = *(u32_t *)(addr_word);
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memcpy((u8_t *)&tmp_word, data_word, remaining);
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nvmc_wait_ready();
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*(u32_t *)addr_word = tmp_word;
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}
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nvmc_wait_ready();
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return 0;
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}
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static int flash_nrf5_erase(struct device *dev, off_t addr, size_t size)
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{
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u32_t pg_size = NRF_FICR->CODEPAGESIZE;
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u32_t n_pages = size / pg_size;
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/* Erase can only be done per page */
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if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
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return -EINVAL;
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}
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if (!is_addr_valid(addr, size)) {
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return -EINVAL;
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}
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if (!n_pages) {
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return 0;
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}
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/* Erase uses a specific configuration register */
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een << NVMC_CONFIG_WEN_Pos;
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nvmc_wait_ready();
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for (u32_t i = 0; i < n_pages; i++) {
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NRF_NVMC->ERASEPAGE = (u32_t)addr + (i * pg_size);
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nvmc_wait_ready();
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}
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
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nvmc_wait_ready();
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return 0;
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}
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static int flash_nrf5_write_protection(struct device *dev, bool enable)
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{
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if (enable) {
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
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} else {
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
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}
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nvmc_wait_ready();
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return 0;
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}
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static const struct flash_driver_api flash_nrf5_api = {
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.read = flash_nrf5_read,
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.write = flash_nrf5_write,
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.erase = flash_nrf5_erase,
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.write_protection = flash_nrf5_write_protection,
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};
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static int nrf5_flash_init(struct device *dev)
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{
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dev->driver_api = &flash_nrf5_api;
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return 0;
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}
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DEVICE_INIT(nrf5_flash, CONFIG_SOC_FLASH_NRF5_DEV_NAME, nrf5_flash_init,
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NULL, NULL, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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