zephyr/boards/st/stm32h745i_disco
Tomáš Juřena d477c66909 boards: st: stm32h745i_disco: Use PLL2Q as FDCAN clock source
With this configuration of the device tree, we use 80 MHz as
a FDCAN bus clock. This configuration allows to pass the tests.

Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
2024-05-20 14:24:05 +03:00
..
doc
support
Kconfig.defconfig
Kconfig.stm32h745i_disco
arduino_r3_connector.dtsi
board.cmake
board.yml
stm32h745i_disco.dtsi
stm32h745i_disco_stm32h745xx_m4.dts
stm32h745i_disco_stm32h745xx_m4.yaml
stm32h745i_disco_stm32h745xx_m4_defconfig
stm32h745i_disco_stm32h745xx_m7.dts boards: st: stm32h745i_disco: Use PLL2Q as FDCAN clock source 2024-05-20 14:24:05 +03:00
stm32h745i_disco_stm32h745xx_m7.yaml boards: st: stm32h745i_disco: Use PLL2Q as FDCAN clock source 2024-05-20 14:24:05 +03:00
stm32h745i_disco_stm32h745xx_m7_defconfig