47 lines
1.3 KiB
C
47 lines
1.3 KiB
C
/*
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* Copyright (c) 2020 Mario Jaun
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
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static const struct arm_mpu_region mpu_regions[] = {
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MPU_REGION_ENTRY("FLASH", CONFIG_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
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MPU_REGION_ENTRY("SRAM", CONFIG_SRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_SRAM_SIZE)),
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/*
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* System memory attributes inhibit the speculative fetch,
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* preventing the RDSERR Flash error
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*/
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MPU_REGION_ENTRY("SYSTEM", 0x1FF00000,
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{ (STRONGLY_ORDERED_SHAREABLE |
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REGION_512K |
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MPU_RASR_XN_Msk | P_RW_U_NA_Msk) }),
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(mac))
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram3))
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MPU_REGION_ENTRY("SRAM3_ETH_BUF",
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DT_REG_ADDR(DT_NODELABEL(sram3)),
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REGION_RAM_NOCACHE_ATTR(REGION_16K)),
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MPU_REGION_ENTRY("SRAM3_ETH_DESC",
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DT_REG_ADDR(DT_NODELABEL(sram3)),
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REGION_PPB_ATTR(REGION_256B)),
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#else
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MPU_REGION_ENTRY("SRAM2_ETH_BUF",
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DT_REG_ADDR(DT_NODELABEL(sram2)),
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REGION_RAM_NOCACHE_ATTR(REGION_16K)),
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MPU_REGION_ENTRY("SRAM2_ETH_DESC",
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DT_REG_ADDR(DT_NODELABEL(sram2)),
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REGION_PPB_ATTR(REGION_256B)),
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#endif
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#endif
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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