36 lines
766 B
C
36 lines
766 B
C
/*
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* Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32C0 processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/linker/linker-defs.h>
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#include <string.h>
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#include <stm32_ll_system.h>
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#include <cmsis_core.h>
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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*/
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void soc_early_init_hook(void)
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{
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/* Enable ART Accelerator I-cache and prefetch */
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LL_FLASH_EnableInstCache();
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LL_FLASH_EnablePrefetch();
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 48 MHz from HSI */
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SystemCoreClock = 48000000;
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}
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