cbaafe209c
The nRF54 and nRF92 chips has data cache, which means the ICMsg and ICBMsg must be configured to follow required cache alignment of the shared memory. The `dcache-alignement` needs to be defined for that. Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no> |
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| .. | ||
| intel,adsp-host-ipc.yaml | ||
| intel,adsp-idc.yaml | ||
| nordic,nrf-ipc.yaml | ||
| nordic,nrf-ipct-common.yaml | ||
| nordic,nrf-ipct-global.yaml | ||
| nordic,nrf-ipct-local.yaml | ||
| zephyr,ipc-icbmsg.yaml | ||
| zephyr,ipc-icmsg-me-follower.yaml | ||
| zephyr,ipc-icmsg-me-initiator.yaml | ||
| zephyr,ipc-icmsg.yaml | ||
| zephyr,ipc-openamp-static-vrings.yaml | ||