61 lines
1.5 KiB
YAML
61 lines
1.5 KiB
YAML
# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
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Takes one of clk_hse, pll2 or clk_hsi as input clock.
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When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
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pll2, configurable prescaler is used.
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Output clock frequency can be computed with the following formula:
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f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
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with, depending on the case:
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f(PLLIN) = f(input_clk) / 2 if input_clk = clk_hsi
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f(PLLIN) = f(input_clk) / PREDIV if input_clk = clk_hse or pll2
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The PLL output frequency must not exceed 72 MHz.
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compatible: "st,stm32f105-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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mul:
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type: int
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required: true
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description: |
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Main PLL multiplication factor for VCO.
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Note: For x6.5 multiplier value, please use "mul = <15>;"
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enum:
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- 4 # x4
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- 5 # x5
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- 6 # x6
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- 7 # x7
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- 8 # x8
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- 9 # x9
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- 15 # x6.5
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prediv:
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type: int
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required: true
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description: |
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Configurable prescaler
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Valid range: 1 - 16
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otgfspre:
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type: boolean
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description: |
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Optional PLL output divisor to generate a 48MHz USB clock.
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When set, PLL output clock is not divided.
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Otherwise, PLL output clock is divided by 1.5.
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