124 lines
2.4 KiB
Plaintext
124 lines
2.4 KiB
Plaintext
/*
|
|
* Copyright (c) 2017-2019 Intel Corporation.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
#include <dt-bindings/interrupt-controller/intel-ioapic.h>
|
|
#include <dt-bindings/pcie/pcie.h>
|
|
|
|
/ {
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "apollo_lake";
|
|
reg = <0>;
|
|
};
|
|
|
|
intc: ioapic@fec00000 {
|
|
compatible = "intel,ioapic";
|
|
reg = <0xfec00000 0x100000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
};
|
|
|
|
flash0: flash@100000{
|
|
compatible = "soc-nv-flash";
|
|
reg = <0x00100000 DT_FLASH_SIZE>;
|
|
};
|
|
|
|
sram0: memory@400000 {
|
|
device_type = "memory";
|
|
compatible = "mmio-sram";
|
|
reg = <0x00400000 DT_SRAM_SIZE>;
|
|
};
|
|
|
|
|
|
soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
|
|
uart0: uart@0 {
|
|
compatible = "ns16550";
|
|
|
|
pcie;
|
|
reg = <PCIE_BDF(0,0x18,0) PCIE_ID(0x8086,0x5abc)>;
|
|
|
|
label = "UART_0";
|
|
clock-frequency = <1843200>;
|
|
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
status = "disabled";
|
|
current-speed = <115200>;
|
|
};
|
|
|
|
uart1: uart@1 {
|
|
compatible = "ns16550";
|
|
|
|
pcie;
|
|
reg = <PCIE_BDF(0,0x18,1) PCIE_ID(0x8086,0x5abe)>;
|
|
|
|
label = "UART_1";
|
|
clock-frequency = <1843200>;
|
|
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
status = "disabled";
|
|
current-speed = <115200>;
|
|
};
|
|
|
|
uart2: uart@2 {
|
|
compatible = "ns16550";
|
|
|
|
pcie;
|
|
reg = <PCIE_BDF(0,0x18,2) PCIE_ID(0x8086,0x5ac0)>;
|
|
|
|
label = "UART_2";
|
|
clock-frequency = <1843200>;
|
|
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
status = "disabled";
|
|
current-speed = <115200>;
|
|
};
|
|
|
|
uart3: uart@3 {
|
|
compatible = "ns16550";
|
|
|
|
pcie;
|
|
reg = <PCIE_BDF(0,0x18,3) PCIE_ID(0x8086,0x5aee)>;
|
|
|
|
label = "UART_3";
|
|
clock-frequency = <1843200>;
|
|
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
status = "disabled";
|
|
current-speed = <115200>;
|
|
};
|
|
|
|
gpio: gpio@d0c50000 {
|
|
compatible = "intel,apl-gpio";
|
|
reg = <0xd0c50000 0x1000>,
|
|
<0xd0c40000 0x1000>,
|
|
<0xd0c70000 0x1000>,
|
|
<0xd0c00000 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "APL_GPIO";
|
|
gpio-controller ;
|
|
#gpio-cells = <2>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|