170 lines
3.1 KiB
Plaintext
170 lines
3.1 KiB
Plaintext
/*
|
|
* Copyright (c) 2018, Synopsys, Inc. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
#include <dt-bindings/i2c/i2c.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
#define DT_APB_CLK_HZ 50000000
|
|
|
|
/ {
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "snps,arcem";
|
|
reg = <1>;
|
|
};
|
|
|
|
intc: arcv2-intc {
|
|
compatible = "snps,arcv2-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
iccm0: iccm@0 {
|
|
device_type = "memory";
|
|
compatible = "arc,iccm";
|
|
};
|
|
|
|
dccm0: dccm@80000000 {
|
|
device_type = "memory";
|
|
compatible = "arc,dccm";
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
|
|
ddr0: memory@10000000 {
|
|
device_type = "memory";
|
|
compatible = "mmio-sram";
|
|
reg = <0x10000000 0x8000000>;
|
|
};
|
|
|
|
|
|
i2c0: i2c@f0004000 {
|
|
compatible = "snps,designware-i2c";
|
|
clock-frequency = <I2C_BITRATE_STANDARD>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xf0004000 0x1000>;
|
|
label = "I2C_0";
|
|
interrupt-parent = <&intc>;
|
|
};
|
|
|
|
i2c1: i2c@f0005000 {
|
|
compatible = "snps,designware-i2c";
|
|
clock-frequency = <I2C_BITRATE_STANDARD>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xf0005000 0x1000>;
|
|
label = "I2C_1";
|
|
interrupt-parent = <&intc>;
|
|
};
|
|
|
|
uart0: uart@f0008000 {
|
|
compatible = "ns16550";
|
|
clock-frequency = <DT_APB_CLK_HZ>;
|
|
reg = <0xf0008000 0x1000>;
|
|
label = "UART_0";
|
|
interrupt-parent = <&intc>;
|
|
};
|
|
|
|
uart1: uart@f0009000 {
|
|
compatible = "ns16550";
|
|
clock-frequency = <DT_APB_CLK_HZ>;
|
|
reg = <0xf0009000 0x1000>;
|
|
label = "UART_1";
|
|
interrupt-parent = <&intc>;
|
|
|
|
};
|
|
|
|
uart2: uart@f000a000 {
|
|
compatible = "ns16550";
|
|
clock-frequency = <DT_APB_CLK_HZ>;
|
|
reg = <0xf000a000 0x1000>;
|
|
label = "UART_2";
|
|
interrupt-parent = <&intc>;
|
|
|
|
};
|
|
|
|
gpio0: gpio@f0002000 {
|
|
compatible = "snps,designware-gpio";
|
|
reg = <0xf0002000 0xc>;
|
|
bits = <32>;
|
|
label = "GPIO_0";
|
|
interrupt-parent = <&intc>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio@f000200c {
|
|
compatible = "snps,designware-gpio";
|
|
reg = <0xf000200c 0xc>;
|
|
bits = <9>;
|
|
label = "GPIO_1";
|
|
interrupt-parent = <&intc>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@f0002018 {
|
|
compatible = "snps,designware-gpio";
|
|
reg = <0xF0002018 0xc>;
|
|
bits = <32>;
|
|
label = "GPIO_2";
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@f0002024 {
|
|
compatible = "snps,designware-gpio";
|
|
reg = <0xF0002024 0xc>;
|
|
bits = <12>;
|
|
label = "GPIO_3";
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
spi0: spi@f0006000 {
|
|
compatible = "snps,designware-spi";
|
|
reg = <0xf0006000 0x1000>;
|
|
label = "SPI_0";
|
|
interrupt-parent = <&intc>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
};
|
|
|
|
spi1: spi@f0007000 {
|
|
compatible = "snps,designware-spi";
|
|
reg = <0xf0007000 0x1000>;
|
|
label = "SPI_1";
|
|
interrupt-parent = <&intc>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
};
|
|
|
|
};
|
|
};
|