zephyr/dts/xtensa/intel
Guennadi Liakhovetski 2a6c70ab19 cavs_v25: switch over to Tigerlake H configuration
Tigerlake H has less RAM and fewer cores. Both should be
supported, selectable at the board level. For now use the H
configuration as more readily available for testing.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2021-01-11 16:10:23 -05:00
..
intel_byt_adsp.dtsi soc/xtensa: Misc. checkpatch fixups 2020-10-21 06:38:53 -04:00
intel_cavs15.dtsi
intel_cavs18.dtsi
intel_cavs20.dtsi
intel_cavs25.dtsi cavs_v25: switch over to Tigerlake H configuration 2021-01-11 16:10:23 -05:00
intel_s1000.dtsi dts: intel_s1000: add GNA node 2021-01-06 05:59:21 -06:00