346 lines
9.2 KiB
ArmAsm
346 lines
9.2 KiB
ArmAsm
/*
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* Copyright (c) 2017, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa-asm2-s.h>
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#include <offsets.h>
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#include <toolchain.h>
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/*
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* xtensa_spill_reg_windows
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*
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* Globally visible symbol to do register spills. Useful for unit
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* testing, or maybe as part of a debug/watchdog/error handler. Not a
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* C function, call this via CALL0 (so you probably have to save off
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* A0, but no other registers need to be spilled). On return, all
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* registers not part of the current function will be spilled to
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* memory.
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*/
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.global xtensa_spill_reg_windows
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.align 4
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xtensa_spill_reg_windows:
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SPILL_ALL_WINDOWS
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ret
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/*
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* xtensa_save_high_regs
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*
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* Call with CALL0, with A2/A3 available as scratch. Pushes the high
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* A4-A15 GPRs to the stack if needed (i.e. if those registers are not
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* part of wrapped-around frames higher up the call stack), returning
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* to the caller with the stack pointer HAVING BEEN MODIFIED to
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* contain them.
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*/
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.global xtensa_save_high_regs
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.align 4
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xtensa_save_high_regs:
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/* Generate a rotated (modulo NREGS/4 bits!) WINDOWSTART in A2
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* by duplicating the bits twice and shifting down by WINDOWBASE
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* bits. Now the LSB is the register quad at WINDOWBASE.
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*/
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rsr.WINDOWSTART a2
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slli a3, a2, (XCHAL_NUM_AREGS / 4)
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or a2, a2, a3
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rsr.WINDOWBASE a3
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ssr a3
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srl a2, a2
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mov a3, a1 /* Stash our original stack pointer */
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/* For the next three bits in WINDOWSTART (which correspond to
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* the A4-A7, A8-A11 and A12-A15 quads), if we find a one,
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* that means that the quad is owned by a wrapped-around call
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* in the registers, so we don't need to spill it or any
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* further registers from the GPRs and can skip to the end.
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*/
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bbsi a2, 1, _high_gpr_spill_done
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addi a1, a1, -16
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s32i a4, a1, 0
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s32i a5, a1, 4
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s32i a6, a1, 8
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s32i a7, a1, 12
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bbsi a2, 2, _high_gpr_spill_done
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addi a1, a1, -16
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s32i a8, a1, 0
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s32i a9, a1, 4
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s32i a10, a1, 8
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s32i a11, a1, 12
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bbsi a2, 3, _high_gpr_spill_done
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addi a1, a1, -16
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s32i a12, a1, 0
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s32i a13, a1, 4
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s32i a14, a1, 8
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s32i a15, a1, 12
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_high_gpr_spill_done:
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/* Push the original stack pointer so we know at restore
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* time how many registers were spilled, then return, leaving the
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* modified SP in A1.
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*/
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addi a1, a1, -4
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s32i a3, a1, 0
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ret
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/*
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* xtensa_restore_high_regs
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*
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* Does the inverse of xtensa_save_high_regs, taking a stack pointer
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* in A1 that resulted and restoring the A4-A15 state (and the stack
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* pointer) to the state they had at the earlier call. Call with
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* CALL0, leaving A2/A3 available as scratch.
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*/
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.global xtensa_restore_high_regs
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.align 4
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xtensa_restore_high_regs:
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/* pop our "original" stack pointer into a2, stash in a3 also */
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l32i a2, a1, 0
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addi a1, a1, 4
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mov a3, a2
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beq a1, a2, _high_restore_done
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addi a2, a2, -16
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l32i a4, a2, 0
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l32i a5, a2, 4
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l32i a6, a2, 8
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l32i a7, a2, 12
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beq a1, a2, _high_restore_done
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addi a2, a2, -16
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l32i a8, a2, 0
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l32i a9, a2, 4
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l32i a10, a2, 8
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l32i a11, a2, 12
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beq a1, a2, _high_restore_done
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addi a2, a2, -16
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l32i a12, a2, 0
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l32i a13, a2, 4
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l32i a14, a2, 8
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l32i a15, a2, 12
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_high_restore_done:
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mov a1, a3 /* Original stack */
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ret
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/*
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* _restore_context
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*
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* Arrive here via a jump. Enters into the restored context and does
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* not return. A1 should have a context pointer in it as received
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* from switch or an interrupt exit. Interrupts must be disabled,
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* and register windows should have been spilled.
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*
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* Note that exit from the restore is done with the RFI instruction,
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* using the EPCn/EPSn registers. Those will have been saved already
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* by any interrupt entry so they are save to use. Note that EPC1 and
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* RFE are NOT usable (they can't preserve PS). Per the ISA spec, all
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* RFI levels do the same thing and differ only in the special
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* registers used to hold PC/PS, but Qemu has been observed to behave
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* strangely when RFI doesn't "return" to a INTLEVEL strictly lower
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* than it started from. So pick level 6 (the highest that works on
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* Qemu, hardware doesn't care so it doesn't matter). In theory we
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* should test to be able to support hardware with less than 6 levels,
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* though...
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*/
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#define RCTX_EPC_REG _CONCAT(EPC, XCHAL_NUM_INTLEVELS)
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#define RCTX_EPS_REG _CONCAT(EPS, XCHAL_NUM_INTLEVELS)
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.global _restore_context
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_restore_context:
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call0 xtensa_restore_high_regs
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l32i a0, a1, BSA_PC_OFF
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wsr.RCTX_EPC_REG a0
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l32i a0, a1, BSA_PS_OFF
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wsr.RCTX_EPS_REG a0
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l32i a0, a1, BSA_SAR_OFF
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wsr.SAR a0
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#if XCHAL_HAVE_LOOPS
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l32i a0, a1, BSA_LBEG_OFF
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wsr.LBEG a0
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l32i a0, a1, BSA_LEND_OFF
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wsr.LEND a0
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l32i a0, a1, BSA_LCOUNT_OFF
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wsr.LCOUNT a0
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#endif
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#if XCHAL_HAVE_S32C1I
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l32i a0, a1, BSA_SCOMPARE1_OFF
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wsr.SCOMPARE1 a0
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#endif
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#if XCHAL_HAVE_THREADPTR && defined(CONFIG_THREAD_LOCAL_STORAGE)
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l32i a0, a1, BSA_THREADPTR_OFF
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wur.THREADPTR a0
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#endif
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rsync
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l32i a0, a1, BSA_A0_OFF
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l32i a2, a1, BSA_A2_OFF
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l32i a3, a1, BSA_A3_OFF
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addi a1, a1, BASE_SAVE_AREA_SIZE
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rfi XCHAL_NUM_INTLEVELS
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/*
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* void xtensa_switch(void *new, void **old_return);
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*
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* Context switches into the prevoiusly-saved "new" handle, placing
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* the saved "old" handle into the address provided by old_return.
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*/
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.global xtensa_switch
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.align 4
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xtensa_switch:
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entry a1, 16
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SPILL_ALL_WINDOWS
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addi a1, a1, -BASE_SAVE_AREA_SIZE
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/* Stash our A0/2/3 and the shift/loop registers into the base
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* save area so they get restored as they are now. A2/A3
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* don't actually get used post-restore, but they need to be
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* stashed across the xtensa_save_high_regs call and this is a
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* convenient place.
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*/
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s32i a0, a1, BSA_A0_OFF
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s32i a2, a1, BSA_A2_OFF
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s32i a3, a1, BSA_A3_OFF
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ODD_REG_SAVE
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/* Stash our PS register contents and a "restore" PC. */
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rsr.PS a0
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s32i a0, a1, BSA_PS_OFF
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movi a0, _switch_restore_pc
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s32i a0, a1, BSA_PC_OFF
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/* Now the high registers */
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call0 xtensa_save_high_regs
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#ifdef CONFIG_KERNEL_COHERENCE
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/* Flush the stack. The top of stack was stored for us in
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* EXCSAVE3 (FIXME: shouldn't be hardcoded!) by arch_cohere_stacks().
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*/
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rsr.EXCSAVE3 a0
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mov a3, a1
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flushloop:
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dhwb a3, 0
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addi a3, a3, XCHAL_DCACHE_LINESIZE
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blt a3, a0, flushloop
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#endif
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/* Restore the A3 argument we spilled earlier (via the base
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* save pointer pushed at the bottom of the stack) and set the
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* stack to the "new" context out of the A2 spill slot.
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*/
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l32i a2, a1, 0
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l32i a3, a2, BSA_A3_OFF
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s32i a1, a3, 0
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/* Switch stack pointer and restore. The jump to
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* _restore_context does not return as such, but we arrange
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* for the restored "next" address to be immediately after for
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* sanity.
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*/
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l32i a1, a2, BSA_A2_OFF
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#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
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call4 z_thread_mark_switched_in
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#endif
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j _restore_context
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_switch_restore_pc:
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retw
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/* Define our entry handler to load the struct kernel_t from the
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* MISC0 special register, and to find the nest and irq_stack values
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* at the precomputed offsets.
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*/
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.align 4
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_handle_excint:
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EXCINT_HANDLER CONFIG_XTENSA_KERNEL_CPU_PTR_SR, ___cpu_t_nested_OFFSET, ___cpu_t_irq_stack_OFFSET
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/* Define the actual vectors for the hardware-defined levels with
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* DEF_EXCINT. These load a C handler address and jump to our handler
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* above.
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*/
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DEF_EXCINT 1, _handle_excint, xtensa_excint1_c
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#if XCHAL_NMILEVEL >= 2
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DEF_EXCINT 2, _handle_excint, xtensa_int2_c
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#endif
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#if XCHAL_NMILEVEL >= 3
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DEF_EXCINT 3, _handle_excint, xtensa_int3_c
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#endif
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#if XCHAL_NMILEVEL >= 4
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DEF_EXCINT 4, _handle_excint, xtensa_int4_c
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#endif
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#if XCHAL_NMILEVEL >= 5
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DEF_EXCINT 5, _handle_excint, xtensa_int5_c
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#endif
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#if XCHAL_NMILEVEL >= 6
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DEF_EXCINT 6, _handle_excint, xtensa_int6_c
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#endif
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#if XCHAL_NMILEVEL >= 7
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DEF_EXCINT 7, _handle_excint, xtensa_int7_c
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#endif
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/* The user exception vector is defined here, as we need to handle
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* MOVSP exceptions in assembly (the result has to be to unspill the
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* caller function of the code that took the exception, and that can't
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* be done in C). A prototype exists which mucks with the stack frame
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* from the C handler instead, but that would add a LARGE overhead to
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* some alloca() calls (those whent he caller has been spilled) just
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* to save these five cycles during other exceptions and L1
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* interrupts. Maybe revisit at some point, with better benchmarking.
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* Note that _xt_alloca_exc is Xtensa-authored code which expects A0
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* to have been saved to EXCSAVE1, which is an unfortunate ABI given
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* that Zephyr code otherwise does not use the EXCSAVE registers.
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*/
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.pushsection .UserExceptionVector.text, "ax"
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.global _Level1RealVector
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_Level1RealVector:
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wsr.excsave1 a0
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rsr.exccause a0
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bnei a0, EXCCAUSE_ALLOCA, _not_alloca
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j _xt_alloca_exc
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_not_alloca:
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rsr.excsave1 a0
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j _Level1Vector
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.popsection
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/* In theory you can have levels up to 15, but known hardware only uses 7. */
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#if XCHAL_NMILEVEL > 7
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#error More interrupts than expected.
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#endif
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/* We don't actually use "kernel mode" currently. Populate the vector
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* out of simple caution in case app code clears the UM bit by mistake.
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*/
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.pushsection .KernelExceptionVector.text, "ax"
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.global _KernelExceptionVector
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_KernelExceptionVector:
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j _Level1Vector
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.popsection
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#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
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.pushsection .DoubleExceptionVector.text, "ax"
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.global _DoubleExceptionVector
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_DoubleExceptionVector:
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#if XCHAL_HAVE_DEBUG
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/* Signals an unhandled double exception */
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1: break 1, 4
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#else
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1:
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#endif
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j 1b
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.popsection
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#endif
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