zephyr/arch/sparc/core
Martin Åberg 53a4acb2dc SPARC: add FPU support
This change adds full shared floating point support for the SPARC
architecture.

All SPARC floating point registers are scratch registers with respect
to function call boundaries. That means we only have to save floating
point registers when switching threads in ISR. The registers are
stored to the corresponding thread stack.

FPU is disabled when calling ISR. Any attempt to use FPU in ISR
will generate the fp_disabled trap which causes Zephyr fatal error.

- This commit adds no new thread state.
- All FPU contest save/restore is synchronous and lazy FPU context
  switch is not implemented.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-04 14:33:43 +02:00
..
offsets
CMakeLists.txt
fatal.c kernel: Cleanup logger setup in kernel files 2020-11-27 09:56:34 -05:00
fault_trap.S
interrupt_trap.S SPARC: add FPU support 2020-12-04 14:33:43 +02:00
irq_manage.c kernel: Cleanup logger setup in kernel files 2020-11-27 09:56:34 -05:00
irq_offload.c
prep_c.c
reset_trap.S
stack_offsets.h SPARC: optimized interrupt stack frame size 2020-12-04 14:33:43 +02:00
sw_trap_set_pil.S
switch.S
thread.c SPARC: add FPU support 2020-12-04 14:33:43 +02:00
tls.c
trap_table_mvt.S
window_trap.S