zephyr/dts/arm/atmel/sam3x.dtsi

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/*
* Copyright (c) 2017 Justin Watson
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4";
reg = <0>;
};
};
sram0: memory@20070000 {
compatible = "mmio-sram";
reg = <0x20070000 0x18000>;
};
flash0: flash@80000 {
compatible = "soc-nv-flash";
label = "FLASH_0";
reg = <0x00080000 0x80000>;
};
soc {
wdog: watchdog@400e1a50 {
compatible = "atmel,sam-watchdog";
reg = <0x400e1a50 0xc>;
interrupts = <4 0>;
peripheral-id = <4>;
label = "WATCHDOG_0";
status = "disabled";
};
i2c0: i2c@4008c000 {
compatible = "atmel,sam-i2c-twi";
clock-frequency = <I2C_BITRATE_STANDARD>;
reg = <0x4008c000 0x128>;
interrupts = <22 0>;
peripheral-id = <22>;
label = "I2C_0";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@40090000 {
compatible = "atmel,sam-i2c-twi";
clock-frequency = <I2C_BITRATE_STANDARD>;
reg = <0x40090000 0x128>;
interrupts = <23 0>;
peripheral-id = <23>;
label = "I2C_1";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
uart0: uart@400e0800 {
compatible = "atmel,sam-uart";
reg = <0x400e0800 0x124>;
interrupts = <8 1>;
peripheral-id = <8>;
status = "disabled";
label = "UART_0";
};
usart0: usart@40098000 {
compatible = "atmel,sam-usart";
reg = <0x40098000 0x130>;
interrupts = <17 0>;
peripheral-id = <17>;
status = "disabled";
label = "USART_0";
};
usart1: usart@4009c000 {
compatible = "atmel,sam-usart";
reg = <0x4009c000 0x130>;
interrupts = <18 0>;
peripheral-id = <18>;
status = "disabled";
label = "USART_1";
};
usart2: usart@400a0000 {
compatible = "atmel,sam-usart";
reg = <0x400a0000 0x130>;
interrupts = <19 0>;
peripheral-id = <19>;
status = "disabled";
label = "USART_2";
};
usart3: usart@400a4000 {
compatible = "atmel,sam-usart";
reg = <0x400a4000 0x130>;
interrupts = <20 0>;
peripheral-id = <20>;
status = "disabled";
label = "USART_3";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};