95 lines
1.9 KiB
Plaintext
95 lines
1.9 KiB
Plaintext
/*
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* Copyright (c) 2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <adi/max32/max32xxx.dtsi>
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#include <zephyr/dt-bindings/dma/max32675_dma.h>
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&flash0 {
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reg = <0x10000000 DT_SIZE_K(384)>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(16)>;
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};
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&clk_inro {
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clock-frequency = <DT_FREQ_K(80)>;
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};
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/delete-node/ &clk_iso;
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/delete-node/ &uart1;
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/* MAX32675 extra peripherals. */
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/ {
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soc {
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sram1: memory@20004000 {
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compatible = "mmio-sram";
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reg = <0x20004000 DT_SIZE_K(16)>;
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};
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sram2: memory@20008000 {
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compatible = "mmio-sram";
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reg = <0x20008000 DT_SIZE_K(32)>;
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};
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sram3: memory@20010000 {
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compatible = "mmio-sram";
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reg = <0x20010000 DT_SIZE_K(64)>;
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};
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sram4: memory@20020000 {
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compatible = "mmio-sram";
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reg = <0x20020000 DT_SIZE_K(4)>;
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};
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sram5: memory@20021000 {
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compatible = "mmio-sram";
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reg = <0x20021000 DT_SIZE_K(4)>;
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};
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sram6: memory@20022000 {
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compatible = "mmio-sram";
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reg = <0x20022000 DT_SIZE_K(8)>;
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};
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sram7: memory@20024000 {
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compatible = "mmio-sram";
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reg = <0x20024000 DT_SIZE_K(16)>;
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};
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dma0: dma@40028000 {
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compatible = "adi,max32-dma";
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reg = <0x40028000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
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interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>;
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dma-channels = <8>;
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status = "disabled";
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#dma-cells = <2>;
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};
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spi1: spi@40047000 {
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compatible = "adi,max32-spi";
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reg = <0x40047000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
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interrupts = <17 0>;
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status = "disabled";
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};
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lptimer0: timer@40114000 {
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compatible = "adi,max32-timer";
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reg = <0x40114000 0x1000>;
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interrupts = <9 0>;
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status = "disabled";
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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prescaler = <1>;
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};
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};
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};
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