79 lines
2.6 KiB
Python
Executable File
79 lines
2.6 KiB
Python
Executable File
#!/usr/bin/env python3
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# Copyright (c) 2022 Intel corporation
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# SPDX-License-Identifier: Apache-2.0
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import sys
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import re
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# Scratch register allocator. Zephyr uses multiple Xtensa SRs as
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# scratch space for various special purposes. Unfortunately the
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# configurable architecture means that not all registers will be the
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# same on every device. This script parses a pre-cooked ("gcc -E
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# -dM") core-isa.h file for the current architecture and assigns
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# registers to usages.
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NEEDED = ("ALLOCA", "CPU", "FLUSH")
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coreisa = sys.argv[1]
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outfile = sys.argv[2]
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syms = {}
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def get(s):
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return syms[s] if s in syms else 0
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with open(coreisa) as infile:
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for line in infile.readlines():
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m = re.match(r"^#define\s+([^ ]+)\s*(.*)", line.rstrip())
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if m:
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syms[m.group(1)] = m.group(2)
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# Use MISC registers first if available, that's what they're for
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regs = [ f"MISC{n}" for n in range(0, int(get("XCHAL_NUM_MISC_REGS"))) ]
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# Next come EXCSAVE. Also record our highest non-debug interrupt level.
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maxint = 0
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for il in range(1, 1 + int(get("XCHAL_NUM_INTLEVELS"))):
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regs.append(f"EXCSAVE{il}")
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if il != int(get("XCHAL_DEBUGLEVEL")):
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maxint = max(il, maxint)
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# Find the highest priority software interrupt. We'll use that for
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# arch_irq_offload().
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irqoff_level = -1
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irqoff_int = -1
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for sym, val in syms.items():
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if val == "XTHAL_INTTYPE_SOFTWARE":
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m = re.match(r"XCHAL_INT(\d+)_TYPE", sym)
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if m:
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intnum = int(m.group(1))
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levelsym = f"XCHAL_INT{intnum}_LEVEL"
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if levelsym in syms:
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intlevel = int(syms[levelsym])
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if intlevel > irqoff_level:
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irqoff_int = intnum
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irqoff_level = intlevel
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# Now emit our output header with the assignments we chose
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with open(outfile, "w") as f:
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f.write("/* Generated File, see gen_zsr.py */\n")
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f.write("#ifndef ZEPHYR_ZSR_H\n")
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f.write("#define ZEPHYR_ZSR_H\n")
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for i, need in enumerate(NEEDED):
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f.write(f"# define ZSR_{need} {regs[i]}\n")
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f.write(f"# define ZSR_{need}_STR \"{regs[i]}\"\n")
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# Emit any remaining registers as generics
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for i in range(len(NEEDED), len(regs)):
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f.write(f"# define ZSR_EXTRA{i - len(NEEDED)} {regs[i]}\n")
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# Also, our highest level EPC/EPS registers
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f.write(f"# define ZSR_RFI_LEVEL {maxint}\n")
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f.write(f"# define ZSR_EPC EPC{maxint}\n")
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f.write(f"# define ZSR_EPS EPS{maxint}\n")
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# And the irq offset interrupt
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if irqoff_int >= 0:
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f.write(f"# define ZSR_IRQ_OFFLOAD_INT {irqoff_int}\n")
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f.write("#endif\n")
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