57 lines
952 B
Plaintext
57 lines
952 B
Plaintext
# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_ARC_HSDK4XD
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config SOC
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default "snps_arc_hsdk4xd"
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config CPU_HS4X
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default y
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config NUM_IRQ_PRIO_LEVELS
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# This processor supports 2 priority levels:
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# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
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default 2
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config NUM_IRQS
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# must be > the highest interrupt number used
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default 88
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config RGF_NUM_BANKS
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# Actually cpu has 4 banks but zephys currently supports up to 2
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default 2
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 500000000
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config ARC_FIRQ
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default y
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config CODE_DENSITY
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default y
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config ARCV2_TIMER_IRQ_PRIORITY
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default 1
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config ARC_CONNECT
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default y
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config MP_MAX_NUM_CPUS
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default 4
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config UART_NS16550_ACCESS_WORD_ONLY
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default y
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depends on UART_NS16550
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config ARC_HAS_ACCL_REGS
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default y
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config ARC_EARLY_SOC_INIT
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default y
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config ARC_HAS_STACK_CHECKING
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default n
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endif # SOC_ARC_HS4XD
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