142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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/* #include <kernel_structs.h> */
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u64_t __start_swap_time;
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u64_t __end_swap_time;
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u64_t __start_intr_time;
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u64_t __end_intr_time;
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u64_t __start_tick_time;
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u64_t __end_tick_time;
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u64_t __end_drop_to_usermode_time;
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/* location of the time stamps*/
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u32_t __read_swap_end_time_value;
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u64_t __common_var_swap_end_time;
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#if CONFIG_ARM
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#include <arch/arm/cortex_m/cmsis.h>
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#endif
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#ifdef CONFIG_NRF_RTC_TIMER
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/* To get current count of timer, first 1 need to be written into
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* Capture Register and Current Count will be copied into corresponding
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* current count register.
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*/
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#define TIMING_INFO_PRE_READ() (NRF_TIMER2->TASKS_CAPTURE[0] = 1)
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#define TIMING_INFO_OS_GET_TIME() (NRF_TIMER2->CC[0])
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#define TIMING_INFO_GET_TIMER_VALUE() (TIMING_INFO_OS_GET_TIME())
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#define SUBTRACT_CLOCK_CYCLES(val) (val)
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#elif CONFIG_X86
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#define TIMING_INFO_PRE_READ()
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#define TIMING_INFO_OS_GET_TIME() (_tsc_read())
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#define TIMING_INFO_GET_TIMER_VALUE() (TIMING_INFO_OS_GET_TIME())
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#define SUBTRACT_CLOCK_CYCLES(val) (val)
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#elif CONFIG_ARM
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#define TIMING_INFO_PRE_READ()
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#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
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#define TIMING_INFO_GET_TIMER_VALUE() (SysTick->VAL)
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#define SUBTRACT_CLOCK_CYCLES(val) (SysTick->LOAD - (u32_t)val)
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#elif CONFIG_ARC
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#define TIMING_INFO_PRE_READ()
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#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
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#define TIMING_INFO_GET_TIMER_VALUE() (_arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT))
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#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
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#elif CONFIG_XTENSA
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#include <xtensa_timer.h>
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#define TIMING_INFO_PRE_READ()
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#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
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#define TIMING_INFO_GET_TIMER_VALUE() (k_cycle_get_32())
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#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
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#elif CONFIG_NIOS2
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#include "altera_avalon_timer_regs.h"
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#define TIMING_INFO_PRE_READ() \
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(IOWR_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE, 10))
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#define TIMING_INFO_OS_GET_TIME() (SUBTRACT_CLOCK_CYCLES(\
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((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) << 16)\
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| ((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE))))
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#define TIMING_INFO_GET_TIMER_VALUE() (\
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((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) << 16)\
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| ((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE)))
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#define SUBTRACT_CLOCK_CYCLES(val) \
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((IORD_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE) \
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<< 16 | \
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(IORD_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE))) \
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- ((u32_t)val))
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#elif CONFIG_RISCV32
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#define TIMING_INFO_PRE_READ()
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#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
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#define TIMING_INFO_GET_TIMER_VALUE() (k_cycle_get_32())
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#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
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#else
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/* Default case */
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#error "Benchmarks have not been implemented for this architecture"
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#endif /* CONFIG_NRF_RTC_TIMER */
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void read_timer_start_of_swap(void)
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{
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if (__read_swap_end_time_value == 1) {
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TIMING_INFO_PRE_READ();
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__start_swap_time = (u32_t) TIMING_INFO_OS_GET_TIME();
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}
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}
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void read_timer_end_of_swap(void)
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{
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if (__read_swap_end_time_value == 1) {
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TIMING_INFO_PRE_READ();
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__read_swap_end_time_value = 2;
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__common_var_swap_end_time = (u64_t)TIMING_INFO_OS_GET_TIME();
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}
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}
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/* ARM processors read current value of time through sysTick timer
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* and nrf soc read it though timer
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*/
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void read_timer_start_of_isr(void)
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{
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TIMING_INFO_PRE_READ();
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__start_intr_time = (u32_t) TIMING_INFO_GET_TIMER_VALUE();
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}
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void read_timer_end_of_isr(void)
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{
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TIMING_INFO_PRE_READ();
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__end_intr_time = (u32_t) TIMING_INFO_GET_TIMER_VALUE();
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}
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void read_timer_start_of_tick_handler(void)
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{
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TIMING_INFO_PRE_READ();
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__start_tick_time = (u32_t)TIMING_INFO_GET_TIMER_VALUE();
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}
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void read_timer_end_of_tick_handler(void)
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{
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TIMING_INFO_PRE_READ();
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__end_tick_time = (u32_t) TIMING_INFO_GET_TIMER_VALUE();
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}
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void read_timer_end_of_userspace_enter(void)
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{
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TIMING_INFO_PRE_READ();
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__end_drop_to_usermode_time = (u32_t) TIMING_INFO_GET_TIMER_VALUE();
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}
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