162 lines
6.5 KiB
C
162 lines
6.5 KiB
C
/*
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* Copyright (c) 2022, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT11XX_H_
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#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT11XX_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/types.h>
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#include "fsl_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MCUX_IMX_ODE_SHIFT 4
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#define MCUX_IMX_PUS_SHIFT 3
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#define MCUX_IMX_PUE_SHIFT 2
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#define MCUX_IMX_DSE_SHIFT 1
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#define MCUX_IMX_SRE_SHIFT 0
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#define MCUX_IMX_PULL_SHIFT 2
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#define MCUX_IMX_PULL_PULLDOWN 0x2
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#define MCUX_IMX_PULL_PULLUP 0x1
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#define MCUX_IMX_PDRV_SHIFT 1
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#define MCUX_IMX_LPSR_ODE_SHIFT 5
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#define MCUX_IMX_SNVS_ODE_SHIFT 6
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#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
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#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
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/*
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* RT11xx has multiple types of register layouts defined for pin configuration
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* registers. There are four types defined:
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* pdrv_pull: registers lack a slew rate and pus field
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* pue_pus: registers have a slew rate and ode field
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* pue_pus_lpsr: in low power state retention domain, shifted ode field
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* pue_pus_snvs: in SNVS domain, shifted ode field
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*/
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#define MCUX_IMX_PUS_PUE 0
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#define MCUX_IMX_PDRV_PULL 1
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#define MCUX_IMX_LPSR 2
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#define MCUX_IMX_SNVS 3
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/*
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* Macro for MCUX_IMX_PULL_NOPULL, which needs to set field to 0x3 if two
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* properties are false
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*/
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#define MCUX_IMX_NOPULL(node_id) \
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((0x2 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 1)) |\
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(0x1 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 0))) \
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#define Z_PINCTRL_MCUX_IMX_PDRV(node_id) \
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IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
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(MCUX_IMX_PULL_PULLDOWN << MCUX_IMX_PULL_SHIFT) |) \
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IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
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(MCUX_IMX_PULL_PULLUP << MCUX_IMX_PULL_SHIFT) |) \
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(MCUX_IMX_NOPULL(node_id) << MCUX_IMX_PULL_SHIFT) | \
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(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_PDRV_SHIFT) | \
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(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \
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(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
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#define Z_PINCTRL_MCUX_IMX_PUE_PUS(node_id) \
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(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \
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((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
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<< MCUX_IMX_PUE_SHIFT) | \
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(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \
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(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \
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(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \
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(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
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#define Z_PINCTRL_MCUX_IMX_LPSR(node_id) \
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(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \
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((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
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<< MCUX_IMX_PUE_SHIFT) | \
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(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \
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(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \
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(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_LPSR_ODE_SHIFT) | \
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(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
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#define Z_PINCTRL_MCUX_IMX_SNVS(node_id) \
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(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \
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((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
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<< MCUX_IMX_PUE_SHIFT) | \
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(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \
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(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \
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(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_SNVS_ODE_SHIFT) | \
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(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
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/* This struct must be present. It is used by the mcux gpio driver */
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struct pinctrl_soc_pinmux {
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uint32_t mux_register; /* IOMUXC SW_PAD_MUX register */
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uint32_t config_register; /* IOMUXC SW_PAD_CTL register */
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uint32_t input_register; /* IOMUXC SELECT_INPUT DAISY register */
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uint32_t gpr_register; /* IOMUXC GPR register */
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uint8_t gpr_shift: 5; /* bitshift for GPR register write */
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uint8_t mux_mode: 4; /* Mux value for SW_PAD_MUX register */
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uint32_t input_daisy:4; /* Mux value for SELECT_INPUT_DAISY register */
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uint8_t gpr_val: 1; /* value to write to GPR register */
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uint8_t pue_mux: 1; /* Is pinmux reg pue type */
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uint8_t pdrv_mux: 1; /* Is pinmux reg pdrv type */
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uint8_t lpsr_mux: 1; /* Is pinmux reg LPSR type */
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uint8_t snvs_mux: 1; /* Is pinmux reg SNVS type */
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};
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struct pinctrl_soc_pin {
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struct pinctrl_soc_pinmux pinmux;
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uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */
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};
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typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
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/* This definition must be present. It is used by the mcux gpio driver */
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#define MCUX_IMX_PINMUX(node_id) \
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{ \
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.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
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.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
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.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
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.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
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.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
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IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 0), \
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(.gpr_register = DT_PROP_BY_IDX(node_id, gpr, 0),)) \
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IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 1), \
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(.gpr_shift = DT_PROP_BY_IDX(node_id, gpr, 1),)) \
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IF_ENABLED(DT_PROP_HAS_IDX(node_id, gpr, 2), \
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(.gpr_val = DT_PROP_BY_IDX(node_id, gpr, 2),)) \
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.pue_mux = DT_PROP(node_id, pin_pue), \
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.pdrv_mux = DT_PROP(node_id, pin_pdrv), \
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.lpsr_mux = DT_PROP(node_id, pin_lpsr), \
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.snvs_mux = DT_PROP(node_id, pin_snvs), \
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}
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#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
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MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
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#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
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{ \
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.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
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IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pue), \
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(.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PUE_PUS(group_id),)) \
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IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pdrv), \
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(.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PDRV(group_id),)) \
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IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_lpsr), \
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(.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_LPSR(group_id),)) \
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IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_snvs), \
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(.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_SNVS(group_id),)) \
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},
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
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DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT11XX_H_ */
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