112 lines
2.7 KiB
ArmAsm
112 lines
2.7 KiB
ArmAsm
/*
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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* Jyunlin Chen <jyunlin.chen@ite.com.tw>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "chip_chipregs.h"
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#include <zephyr/toolchain.h>
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/* exports */
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GTEXT(__start)
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/* imports */
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GTEXT(__initialize)
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GTEXT(_isr_wrapper)
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SECTION_FUNC(vectors, __start)
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#ifdef CONFIG_RISCV_GP
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.option push
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.option norelax
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/* Configure the GP register */
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la gp, __global_pointer$
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.option pop
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#endif
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.option norvc;
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#ifdef CONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE
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/* Enable JTAG debug interface */
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la t0, IT8XXX2_GCTRL_PMER3
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lb t1, 0(t0)
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ori t1, t1, IT8XXX2_GCTRL_JTAG
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sb t1, 0(t0)
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la t0, IT8XXX2_JTAG_PINS_BASE
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li t1, 0
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/* Configure GPIOA0 as TCK function */
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sb t1, 0(t0)
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/* Configure GPIOA1 as TDI function */
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sb t1, 1(t0)
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/* Configure GPIOA4 as TDO function */
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sb t1, 4(t0)
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/* Configure GPIOA5 as TMS function */
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sb t1, 5(t0)
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/* Configure GPIOA6 as TRST function */
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sb t1, 6(t0)
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/* I/O voltage is 3.3V */
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la t0, IT8XXX2_JTAG_VOLT_SET
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sb t1, 0(t0)
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#endif
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/*
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* Set mtvec (Machine Trap-Vector Base-Address Register)
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* to _isr_wrapper.
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*/
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la t0, _isr_wrapper
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csrw mtvec, t0
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csrwi mie, 0
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#if (CONFIG_SOC_IT8XXX2_FLASH_SIZE_BYTES == 0x100000)
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/*
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* bit[3-0]@EIDSR=8: instruction local memory size is 1M byte
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* This operation must be done before accessing memory.
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*/
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la t0, IT8XXX2_GCTRL_EIDSR
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lb t1, 0(t0)
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andi t1, t1, 0xf0
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ori t1, t1, 0x8
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sb t1, 0(t0)
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#endif
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/* Jump to __initialize */
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tail __initialize
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/*
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* eflash signature used to enable specific function after power-on reset.
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* (HW mechanism)
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* The content of 16-bytes must be the following and at offset 0x80 of binary.
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* ----------------------------------------------------------------------------
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* 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th
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* ----------------------------------------------------------------------------
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* A5h A5h A5h A5h A5h A5h [host] [flag] 85h 12h 5Ah 5Ah AAh AAh 55h 55h
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* ----------------------------------------------------------------------------
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* [host]: A4h = enable eSPI, A5h = enable LPC
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* [flag]:
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* bit7: it must be 1b.
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* bit6: it must be 0b.
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* bit5: it must be 1b.
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* bit4: 1b = 32.768KHz is from the internal clock generator.
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* bit3: it must be 0b.
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* bit2: it must be 1b.
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* bit1: it must be 0b.
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* bit0: it must be 0b.
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*/
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.org 0x80
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.balign 16
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.global eflash_sig
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eflash_sig:
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.byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
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#ifdef CONFIG_ESPI
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.byte 0xA4 /* enable eSPI */
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#else
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.byte 0xA5 /* enable LPC */
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#endif
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/* flag of signature */
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#ifdef CONFIG_SOC_IT8XXX2_EXT_32K
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.byte 0xA4 /* use external 32.768 kHz oscillator */
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#else
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.byte 0xB4 /* enable internal clock generator */
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#endif
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.byte 0x85, 0x12, 0x5A, 0x5A, 0xAA, 0xAA, 0x55, 0x55
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