zephyr/doc/services/llext
Eric Ackermann 5275d44409 llext: Add RISC-V arch-specific relocations
This commit introduces architecture-specific ELF relocations for RISC-V,
in accordance with the RISC-V PSABI specification:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
Also, the necessary compiler configurations for compiling LLEXT
extensions on RISC-V are added, and the llext tests are executed on
RISC-V targets.
Calling llext extensions from user threads in RISC-V is still
unsupported as of this commit.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
2024-10-03 21:59:42 +01:00
..
api.rst
build.rst
config.rst
index.rst llext: Add RISC-V arch-specific relocations 2024-10-03 21:59:42 +01:00
load.rst