263 lines
7.1 KiB
C
263 lines
7.1 KiB
C
/* Freescale K20 microprocessor UART register definitions */
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @brief Contains the UART Registers for the K20 Family of microprocessors.
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*/
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#ifndef _K20UART_H_
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#define _K20UART_H_
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#include <stdint.h>
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#include <misc/__assert.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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union BDH {
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uint8_t value;
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struct {
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uint8_t sbr : 5 __packed; /* Hi Baud Rate Bits */
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uint8_t res_5 : 1 __packed;
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uint8_t rx_edge_int_en : 1 __packed; /* RxD Active Edge */
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uint8_t lbkd_int_en : 1 __packed; /* LIN Break Detect */
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} field;
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}; /* 0x000 BaudRate High */
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union C1 {
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uint8_t value;
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struct {
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uint8_t odd_parity : 1 __packed;
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uint8_t parity_enable : 1 __packed;
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uint8_t idle_line_type : 1 __packed;
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uint8_t rx_wakep_method : 1 __packed;
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uint8_t mode9bit : 1 __packed;
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uint8_t remote_loopback : 1 __packed;
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uint8_t uart_stop_wait : 1 __packed;
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uint8_t loopback_en : 1 __packed;
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} field;
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}; /* 0x002 Control 1 */
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#define RX_EN_MASK 0x04
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#define TX_EN_MASK 0x08
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union C2 {
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uint8_t value;
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struct {
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uint8_t send_break : 1 __packed;
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uint8_t rx_wakeup_ctrl : 1 __packed;
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uint8_t rx_enable : 1 __packed;
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uint8_t tx_enable : 1 __packed;
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uint8_t idle_line_int_en : 1 __packed;
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uint8_t rx_full_int_dma_tx_en : 1 __packed;
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uint8_t tx_complete_int_en : 1 __packed;
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uint8_t tx_int_dma_tx_en : 1 __packed;
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} field;
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}; /* 0x003 Control 2 */
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union C3 {
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uint8_t value;
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struct {
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uint8_t parity_err_int_en : 1 __packed;
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uint8_t frame_err_int_en : 1 __packed;
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uint8_t noise_err_int_en : 1 __packed;
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uint8_t overrun_err_int_en : 1 __packed;
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uint8_t tx_data_invert : 1 __packed;
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uint8_t tx_data_pin_outt_dir : 1 __packed;
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uint8_t tx_bit8 : 1 __packed;
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uint8_t rx_bit8 : 1 __packed;
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} field;
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}; /* 0x006 Control 3 */
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union C4 {
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uint8_t value;
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struct {
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uint8_t brfa : 5 __packed; /* BaudRateFineAdjust*/
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uint8_t mode10bit : 1 __packed;
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uint8_t matech_addr_mode1_en : 1 __packed;
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uint8_t match_addr_mode2_en : 1 __packed;
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} field;
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}; /* 0x00A Control 4 */
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#define TX_DATA_EMPTY_MASK 0x80
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#define RX_DATA_FULL_MASK 0x20
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union S1 {
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uint8_t value;
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struct {
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uint8_t parity_err : 1 __packed;
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uint8_t framing_err : 1 __packed;
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uint8_t noice : 1 __packed;
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uint8_t rx_overrun : 1 __packed;
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uint8_t idle_line : 1 __packed;
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uint8_t rx_data_full : 1 __packed;
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uint8_t tx_complete : 1 __packed;
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uint8_t tx_data_empty : 1 __packed;
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} field;
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}; /* 0x004 Status 1 */
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union S2 {
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uint8_t value;
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struct e {
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uint8_t rx_active : 1 __packed;
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uint8_t lin_bk_detect_en : 1 __packed;
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uint8_t brk_char_len13 : 1 __packed;
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uint8_t rx_wakeup_idle_detect : 1 __packed;
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uint8_t rx_data_inverted : 1 __packed;
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uint8_t msb_first : 1 __packed;
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uint8_t rxedgif : 1 __packed;
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uint8_t lbkdif : 1 __packed;
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} field;
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}; /* 0x005 Status 2 */
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#define FIFO_SIZE_1 0
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#define FIFO_SIZE_4 1
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#define FIFO_SIZE_8 2
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#define FIFO_SIZE_16 3
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#define FIFO_SIZE_32 4
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#define FIFO_SIZE_64 5
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#define FIFO_SIZE_128 6
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#define FIFO_SIZE_RES 6 /* Reserved size */
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#define RX_FIFO_EN_MASK 0x08
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#define TX_FIFO_EN_MASK 0x80
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union PFIFO {
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uint8_t value;
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struct {
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uint8_t rx_fifo_size : 3 __packed; /* read-only */
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uint8_t rx_fifo_en : 1 __packed;
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uint8_t tx_fifo_size : 3 __packed; /* read-only */
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uint8_t tx_fifo_en : 1 __packed;
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} field;
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}; /* 0x010 Fifo Parameter 1 */
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#define RX_FIFO_FLUSH_MASK 0x40
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#define TX_FIFO_FLUSH_MASK 0x80
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union CFIFO {
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uint8_t value;
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struct {
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uint8_t rx_fifo_underflow_int_en : 1 __packed;
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uint8_t tx_fifo_overflow_int_en : 1 __packed;
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uint8_t rx_fifo_overflow_int_en : 1 __packed;
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uint8_t res_3 : 3 __packed;
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uint8_t rx_fifo_flush : 1 __packed; /* write-only */
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uint8_t tx_fifo_flush : 1 __packed; /* write-only */
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} field;
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}; /* 0x011 Fifo Control */
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struct K20_UART {
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union BDH bdh; /* 0x000 Baud Rate High */
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uint8_t bdl; /* 0x001 Baud Rate Low (04)*/
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union C1 c1; /* 0x002 Control 1 */
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union C2 c2; /* 0x003 Control 2 */
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union S1 s1; /* 0x004 Status 1 (C0) RO*/
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union S2 s2; /* 0x005 Status 2 */
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union C3 c3; /* 0x006 Control 3 */
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uint8_t d; /* 0x007 Data */
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uint8_t ma1; /* 0x008 Match Address 1 */
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uint8_t ma2; /* 0x009 Match Address 1 */
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union C4 c4; /* 0x00A Control 4 */
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uint8_t c5; /* 0x00B Control 5 */
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uint8_t ed; /* 0x00C Extended Data */
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uint8_t modem; /* 0x00D Modem */
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uint8_t ir; /* 0x00E Infrared */
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uint8_t z_reserved00f; /* 0x00F */
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union PFIFO pfifo; /* 0x010 FIFO Param */
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union CFIFO cfifo; /* 0x011 FIFO Control */
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uint8_t sfifo; /* 0x012 FIFO Status (C0)*/
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uint8_t twfifo; /* 0x013 FIFO Tx Watermark */
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uint8_t tcfifo; /* 0x014 FIFO Tx Count */
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uint8_t rwfifo; /* 0x015 FIFO Rx Watermark (01)*/
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uint8_t rcfifo; /* 0x016 FIFO Rx Count */
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uint8_t u_7816[0x20 - 0x17]; /* 0x017-0x1F UART ISO-7816 standard */
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uint8_t u_cea709_1[0x32 - 0x20]; /* 0x020-0x31 UART CEA8709.1 standard*/
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/* 0x032-0xFFF Reserved */
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uint8_t z_reserv_statused038_03c[0x1000 - 0x32];
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}; /* K20 Microntroller UART module */
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/**
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* @brief Set baud rate for K20 UART port.
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*
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* @param uart_p UART data
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* @param clk_freq Clock frequency
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* @param baud_rate Baud rate to set
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void _uart_k20_baud_rate_set(volatile struct K20_UART *u,
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uint32_t clk_freq,
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uint32_t baud_rate)
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{
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/* avoid divide by zero */
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if ((baud_rate == 0) || (clk_freq == 0)) {
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return;
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}
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/*
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* The baud rate is calculated as:
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* baud_rate = clk_freq/(16*(SBR[12:0]+BRFA[5:0]/32)), where
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* - SBR is the combined UART Baud Rate Register settings and
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* - BRFA is the UART Baud Rate Fine Adjustment setting
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* This is equivalent to:
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* 32xSBR + BRFA = 2 * clkFreq/baudRate
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*/
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uint32_t clk_br = 2 * clk_freq / baud_rate;
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uint16_t sbr = clk_br >> 5;
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uint8_t brfa = clk_br - (sbr << 5);
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__ASSERT((sbr && 0x1FFF),
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"clk_freq is too high or baud_rate is too low");
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/* Note there are other fields (interrupts flag) in BDH register */
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u->bdh.field.sbr = (uint8_t)(sbr >> 8);
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u->bdl = (uint8_t)(sbr & 0xFF);
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u->c4.field.brfa = brfa;
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}
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/**
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* @brief Enable FIFO for K20 UART port
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*
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* @param uart_p UART data
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*
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* @return N/A
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*/
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static inline void _uart_k20_fifo_enable(volatile struct K20_UART *uart_p)
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{
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uint8_t tx_rx_state = uart_p->c2.value && (TX_EN_MASK | RX_EN_MASK);
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/* disable Rx and Tx */
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uart_p->c2.value &= ~(TX_EN_MASK | RX_EN_MASK);
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uart_p->pfifo.value |= (TX_FIFO_EN_MASK | RX_FIFO_EN_MASK);
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uart_p->cfifo.value |= (TX_FIFO_FLUSH_MASK | RX_FIFO_FLUSH_MASK);
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/* restore Rx and Tx */
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uart_p->c2.value |= tx_rx_state;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _K20UART_H_ */
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