97 lines
2.8 KiB
C
97 lines
2.8 KiB
C
/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/zephyr.h>
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#include <soc.h>
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#include <zephyr/storage/flash_map.h>
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#include <esp_log.h>
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#include <esp32/rom/cache.h>
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#include <soc/dport_reg.h>
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#include <bootloader_flash_priv.h>
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
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extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
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extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
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void __start(void);
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static HDR_ATTR void (*_entry_point)(void) = &__start;
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static int map_rom_segments(void)
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{
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int rc = 0;
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size_t _partition_offset = FLASH_AREA_OFFSET(image_0);
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uint32_t _app_irom_start = _partition_offset +
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(uint32_t)&_image_irom_start;
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uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
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uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr;
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uint32_t _app_drom_start = _partition_offset +
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(uint32_t)&_image_drom_start;
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uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
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uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr;
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Cache_Read_Disable(0);
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Cache_Flush(0);
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/* Clear the MMU entries that are already set up,
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* so the new app only has the mappings it creates.
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*/
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for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
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DPORT_PRO_FLASH_MMU_TABLE[i] =
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DPORT_FLASH_MMU_TABLE_INVALID_VAL;
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}
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uint32_t drom_vaddr_addr_aligned = _app_drom_vaddr & MMU_FLASH_MASK;
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uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size,
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_app_drom_vaddr);
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rc = cache_flash_mmu_set(0, 0, drom_vaddr_addr_aligned, _app_drom_start
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& MMU_FLASH_MASK, 64, drom_page_count);
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rc |= cache_flash_mmu_set(1, 0, drom_vaddr_addr_aligned, _app_drom_start
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& MMU_FLASH_MASK, 64, drom_page_count);
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uint32_t irom_vaddr_addr_aligned = _app_irom_vaddr & MMU_FLASH_MASK;
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uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size,
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_app_irom_vaddr);
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rc |= cache_flash_mmu_set(0, 0, irom_vaddr_addr_aligned, _app_irom_start
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& MMU_FLASH_MASK, 64, irom_page_count);
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rc |= cache_flash_mmu_set(1, 0, irom_vaddr_addr_aligned, _app_irom_start
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& MMU_FLASH_MASK, 64, irom_page_count);
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DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG,
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(DPORT_PRO_CACHE_MASK_IRAM0) |
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(DPORT_PRO_CACHE_MASK_IRAM1 & 0) |
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(DPORT_PRO_CACHE_MASK_IROM0 & 0) |
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DPORT_PRO_CACHE_MASK_DROM0 |
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DPORT_PRO_CACHE_MASK_DRAM1);
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG,
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(DPORT_APP_CACHE_MASK_IRAM0) |
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(DPORT_APP_CACHE_MASK_IRAM1 & 0) |
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(DPORT_APP_CACHE_MASK_IROM0 & 0) |
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DPORT_APP_CACHE_MASK_DROM0 |
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DPORT_APP_CACHE_MASK_DRAM1);
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esp_rom_Cache_Read_Enable(0);
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return rc;
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}
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#endif
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void __start(void)
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{
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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int err = map_rom_segments();
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if (err != 0) {
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ets_printf("Failed to setup XIP, aborting\n");
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abort();
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}
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#endif
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__esp_platform_start();
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}
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