63 lines
1.6 KiB
C
63 lines
1.6 KiB
C
/*
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* Copyright (c) 2016 Piotr Mienkowski
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief System module to support early Atmel SAM E70 MCU configuration
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/arch/cpu.h>
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/**
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* @brief Perform SoC configuration at boot.
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*
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* This should be run early during the boot process but after basic hardware
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* initialization is done.
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*
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* @return 0
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*/
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static int atmel_same70_config(const struct device *dev)
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{
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#ifdef CONFIG_SOC_ATMEL_SAME70_DISABLE_ERASE_PIN
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/* Disable ERASE function on PB12 pin, this is controlled by Bus Matrix */
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MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
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#endif
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/* In Cortex-M based SoCs JTAG interface can be used to perform
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* IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug
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* interface therefore there is no harm done by disabling the JTAG TDI
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* pin by default.
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*/
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/* Disable TDI function on PB4 pin, this is controlled by Bus Matrix */
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MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4;
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#ifdef CONFIG_LOG_BACKEND_SWO
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/* Disable PCK3 clock used by ETM module */
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PMC->PMC_SCDR = PMC_SCDR_PCK3;
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while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) {
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;
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}
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/* Select PLLA clock as PCK3 clock */
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PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK;
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/* Enable PCK3 clock */
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PMC->PMC_SCER = PMC_SCER_PCK3;
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/* Wait for PCK3 setup to complete */
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while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) {
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;
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}
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/* Enable TDO/TRACESWO function on PB5 pin */
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MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5;
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#else
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/* Disable TDO/TRACESWO function on PB5 pin */
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MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
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#endif
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return 0;
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}
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SYS_INIT(atmel_same70_config, PRE_KERNEL_1, 1);
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