254 lines
6.2 KiB
C
254 lines
6.2 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file Driver for DesignWare PWM driver.
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*
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* The timer IP block can act as both timer and PWM. Under PWM mode, each port
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* has two registers to specify how long to stay low, and how long to stay high.
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* Care must be taken so that PWM and timer functions are not both enabled
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* on one port.
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*
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* The set of registers for each timer repeats every 0x14.
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* However, the load count 2 starts at 0xB0, and repeats every 0x04.
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* Accessing load count 2 registers, thus, requires some special treatment.
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*/
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#include <nanokernel.h>
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#include <pwm.h>
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/* Register for component version */
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#define REG_COMP_VER 0xAC
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/* Timer Load Count register, for pin to stay low. */
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#define REG_TMR_LOAD_CNT 0x00
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/* Control for timer */
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#define REG_TMR_CTRL 0x08
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/* Offset from Timer 1 Load Count address
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* for other timers. (e.g. Timer 2 address +0x14,
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* timer 3 address + 0x28, etc.)
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*
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* This also applies to other registers for
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* different timers (except load count 2).
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*/
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#define REG_OFFSET 0x14
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/* Timer Load Count 2 register, for pin to stay high. */
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#define REG_TMR_LOAD_CNT2 0xB0
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/* Offset from Timer 1 Load Count 2 address
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* for other timers. (e.g. Timer 2 address +0x04,
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* timer 3 address + 0x08, etc.)
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*/
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#define REG_OFFSET_LOAD_CNT2 0x04
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/* Default for control register:
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* PWM mode, interrupt masked, user-defined count mode, but disabled
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*/
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#define TIMER_INIT_CTRL 0x0E
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struct pwm_dw_config {
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/** Base address of registers */
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uint32_t addr;
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/** Number of ports */
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uint32_t num_ports;
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};
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/**
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* Find the base address for each timer
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*
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* @param dev Device struct
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* @param timer Which timer
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*
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* @return The base address of that particular timer
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*/
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static inline int pwm_dw_timer_base_addr(struct device *dev, uint32_t timer)
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{
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struct pwm_dw_config * const cfg =
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(struct pwm_dw_config *)dev->config->config_info;
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return (cfg->addr + (timer * REG_OFFSET));
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}
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/**
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* Find the load count 2 address for each timer
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*
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* @param dev Device struct
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* @param timer Which timer
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*
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* @return The load count 2 address of that particular timer
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*/
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static inline int pwm_dw_timer_ldcnt2_addr(struct device *dev, uint32_t timer)
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{
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struct pwm_dw_config * const cfg =
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(struct pwm_dw_config *)dev->config->config_info;
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return (cfg->addr + REG_TMR_LOAD_CNT2 + (timer * REG_OFFSET_LOAD_CNT2));
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}
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static int pwm_dw_configure(struct device *dev, int access_op,
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uint32_t pwm, int flags)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(access_op);
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ARG_UNUSED(pwm);
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ARG_UNUSED(flags);
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return DEV_OK;
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}
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static int __set_one_port(struct device *dev, uint32_t pwm,
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uint32_t on, uint32_t off)
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{
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uint32_t reg_addr;
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reg_addr = pwm_dw_timer_base_addr(dev, pwm);
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/* Disable timer to prevent any output */
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sys_write32(TIMER_INIT_CTRL, (reg_addr + REG_TMR_CTRL));
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if ((off == 0) || (on == 0)) {
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/* stop PWM if so specified */
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return DEV_OK;
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}
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/* write timer for pin to stay low */
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sys_write32(off, (reg_addr + REG_TMR_LOAD_CNT));
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/* write timer for pin to stay high */
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sys_write32(on, pwm_dw_timer_ldcnt2_addr(dev, pwm));
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/* Enable timer so it starts running and counting */
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sys_write32((TIMER_INIT_CTRL | 0x01), (reg_addr + REG_TMR_CTRL));
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return DEV_OK;
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}
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/**
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* Set the duration for on/off timer of PWM.
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*
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* This sets the duration for the pin to low or high.
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*
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* Assumes a nominal system clock of 32MHz, each count of on/off represents
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* 31.25ns (e.g. on == 2 means the pin stays high for 62.5ns).
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* The duration of 1 count depends on system clock. Refer to the hardware
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* manual for more information.
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*
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* @param dev Device struct
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* @param access_op whether to set one pin or all
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* @param pwm Which PWM port to set, 0 if addressing all
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* @param on Duration for pin to stay high (must be >= 2)
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* @param off Duration for pin to stay low (must be >= 2)
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*
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* @return DEV_OK
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*/
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static int pwm_dw_set_values(struct device *dev, int access_op,
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uint32_t pwm, uint32_t on, uint32_t off)
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{
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struct pwm_dw_config * const cfg =
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(struct pwm_dw_config *)dev->config->config_info;
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int i;
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switch (access_op) {
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case PWM_ACCESS_BY_PIN:
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/* make sure the PWM port exists */
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if (pwm >= cfg->num_ports) {
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return DEV_FAIL;
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}
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return __set_one_port(dev, pwm, on, off);
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case PWM_ACCESS_ALL:
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for (i = 0; i < cfg->num_ports; i++) {
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__set_one_port(dev, i, on, off);
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}
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return DEV_OK;
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}
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return DEV_INVALID_OP;
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}
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static int pwm_dw_set_duty_cycle(struct device *dev, int access_op,
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uint32_t pwm, uint8_t duty)
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{
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/* The IP block does not natively support duty cycle settings.
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* So need to use set_values().
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**/
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ARG_UNUSED(dev);
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ARG_UNUSED(access_op);
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ARG_UNUSED(pwm);
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ARG_UNUSED(duty);
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return DEV_INVALID_OP;
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}
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static int pwm_dw_suspend(struct device *dev)
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{
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ARG_UNUSED(dev);
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return DEV_INVALID_OP;
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}
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static int pwm_dw_resume(struct device *dev)
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{
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ARG_UNUSED(dev);
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return DEV_INVALID_OP;
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}
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static struct pwm_driver_api pwm_dw_drv_api_funcs = {
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.config = pwm_dw_configure,
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.set_values = pwm_dw_set_values,
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.set_duty_cycle = pwm_dw_set_duty_cycle,
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.suspend = pwm_dw_suspend,
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.resume = pwm_dw_resume,
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};
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/**
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* @brief Initialization function of PCA9685
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*
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* @param dev Device struct
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* @return DEV_OK if successful, failed otherwise.
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*/
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int pwm_dw_init(struct device *dev)
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{
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dev->driver_api = &pwm_dw_drv_api_funcs;
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return DEV_OK;
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}
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/* Initialization for PWM_DW */
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#if defined(CONFIG_PWM_DW)
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#include <device.h>
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#include <init.h>
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static struct pwm_dw_config pwm_dw_cfg = {
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.addr = CONFIG_PWM_DW_BASE_ADDR,
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.num_ports = CONFIG_PWM_DW_NUM_PORTS,
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};
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DEVICE_INIT(pwm_dw_0, CONFIG_PWM_DW_DEV_NAME, pwm_dw_init,
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NULL, &pwm_dw_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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#endif /* CONFIG_PWM_DW */
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