zephyr/arch/xtensa
Sathish Kuttan 824bcaca52 xtensa: intel_s1000: Add SoC level SYS_INIT
Added a SYS_INIT for SoC level initialization of Intel S1000
Added routines for setting up resource ownership for
    DMA, I2S
Added routine to setup power gating and clock configuration

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-08-19 11:06:09 -07:00
..
core esp32: update to ESP-IDF v3.0-dev-2648-gb2ff235b 2018-06-13 18:53:43 -04:00
include esp32: update to ESP-IDF v3.0-dev-2648-gb2ff235b 2018-06-13 18:53:43 -04:00
soc xtensa: intel_s1000: Add SoC level SYS_INIT 2018-08-19 11:06:09 -07:00
CMakeLists.txt cmake: LD: Specify the entry point in the linker scripts 2018-07-03 17:18:14 -04:00
Kconfig Kconfig: Switch to improved globbing statements 2018-08-15 04:07:44 -07:00