f4a0ea7b43
This got broken during the cpu_init unification pass. I appear to
have copied that zero out of code that initialized Zephyr on a
uniprocessor config somewhere. But what it means is that any use of
the S32C1I instruction to store to any memory type will trap an
exception! And even when CONFIG_MP_NUM_CPUS==1, we will emit code to
do that in the atomics layer when SMP=y.
That configuration ("SMP" with 1 cpu) is actually exercised by some
tests, including important ones like timer_api. These got broken.
Fix.
Really it's never correct to have anything but 1:1:1 ("external RCW
transaction") on these CPUs. All Intel cAVS processors have hardware
atomics support. We owe it to all the code we'll run to make sure it
works as documented and doesn't explode.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
|
||
|---|---|---|
| .. | ||
| esp32 | ||
| esp32s2 | ||
| intel_adsp | ||
| intel_s1000 | ||
| nxp_adsp | ||
| sample_controller | ||
| CMakeLists.txt | ||