96 lines
2.0 KiB
Plaintext
96 lines
2.0 KiB
Plaintext
/*
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* Copyright 2022 Huawei France Technologies SASU
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <mem.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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};
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cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x100>;
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};
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cpu@5 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x101>;
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};
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};
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gic: interrupt-controller@fee00000 {
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#address-cells = <1>;
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0xfee00000 0x10000>, /* GICD */
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<0xfef00000 0xc0000>, /* GICR */
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<0xfff00000 0x10000>, /* GICC */
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<0xfff10000 0x10000>, /* GICH */
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<0xfff20000 0x10000>; /* GICV */
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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sram0: memory@10000000 {
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reg = <0x10000000 DT_SIZE_M(128)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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uart2: serial@ff1a0000 {
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compatible = "rockchip,rk3399-uart", "ns16550";
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reg = <0xff1a0000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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reg-shift = <2>;
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clock-frequency = <350000000>;
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};
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};
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