8185faa0cb
On S32K344, the offset in memory map between each channel is 0x4000 for most channels, but there is specific case is between channel 11 and 12 which is 0x1D4000 instead. As a consequence, 32 channels are divided to two parts: one starts from channel 0 -> 11. The other is from channel 128 to 145. The channel gap is from 12 -> 127. For user and data structures in shim driver, the channel's value comes from 0 --> 31. Above constraint will be counted when interact with the mcux sdk Beside that, the DMAMUX register in this platform is very specific, not in identical with DMAMUX channel, so shim driver is updated to cover this case Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com> |
||
|---|---|---|
| .. | ||
| acsip | ||
| ambiq | ||
| aspeed | ||
| atmel | ||
| broadcom | ||
| cypress | ||
| gigadevice | ||
| infineon | ||
| intel_socfpga_std | ||
| microchip | ||
| nordic | ||
| nuvoton | ||
| nxp | ||
| olimex | ||
| quicklogic | ||
| renesas | ||
| rpi_pico | ||
| seeed | ||
| silabs | ||
| st | ||
| ti | ||
| xilinx | ||
| armv6-m.dtsi | ||
| armv7-a.dtsi | ||
| armv7-m.dtsi | ||
| armv7-r.dtsi | ||
| armv8-m.dtsi | ||
| armv8-r.dtsi | ||
| armv8.1-m.dtsi | ||