473 lines
11 KiB
C
473 lines
11 KiB
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifive_gpio0
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/**
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* @file GPIO driver for the SiFive Freedom Processor
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <soc.h>
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#include <drivers/gpio.h>
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#include <sys/util.h>
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#include "gpio_utils.h"
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typedef void (*sifive_cfg_func_t)(void);
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/* sifive GPIO register-set structure */
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struct gpio_sifive_t {
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unsigned int in_val;
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unsigned int in_en;
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unsigned int out_en;
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unsigned int out_val;
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unsigned int pue;
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unsigned int ds;
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unsigned int rise_ie;
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unsigned int rise_ip;
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unsigned int fall_ie;
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unsigned int fall_ip;
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unsigned int high_ie;
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unsigned int high_ip;
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unsigned int low_ie;
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unsigned int low_ip;
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unsigned int iof_en;
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unsigned int iof_sel;
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unsigned int invert;
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};
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struct gpio_sifive_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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uintptr_t gpio_base_addr;
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/* multi-level encoded interrupt corresponding to pin 0 */
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uint32_t gpio_irq_base;
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sifive_cfg_func_t gpio_cfg_func;
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};
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struct gpio_sifive_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* list of callbacks */
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sys_slist_t cb;
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};
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/* Helper Macros for GPIO */
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#define DEV_GPIO_CFG(dev) \
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((const struct gpio_sifive_config * const)(dev)->config_info)
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#define DEV_GPIO(dev) \
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((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
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#define DEV_GPIO_DATA(dev) \
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((struct gpio_sifive_data *)(dev)->driver_data)
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/* _irq_level and _level2_irq are copied from
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* soc/riscv/riscv-privileged/common/soc_common_irq.c
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* Ideally this kind of thing should be made available in include/irq.h or
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* somewhere similar since the multi-level IRQ format is generic to
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Zephyr, and then both this copy and the one in riscv-privileged
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* be removed for the shared implementation
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*/
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static inline unsigned int _irq_level(unsigned int irq)
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{
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return ((irq >> 8) && 0xff) == 0U ? 1 : 2;
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}
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static inline unsigned int _level2_irq(unsigned int irq)
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{
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return (irq >> 8) - 1;
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}
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/* Given gpio_irq_base and the pin number, return the IRQ number for the pin */
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static inline unsigned int gpio_sifive_pin_irq(unsigned int base_irq, int pin)
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{
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unsigned int level = _irq_level(base_irq);
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unsigned int pin_irq = 0;
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if (level == 1) {
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pin_irq = base_irq + pin;
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} else if (level == 2) {
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pin_irq = base_irq + (pin << 8);
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}
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return pin_irq;
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}
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/* Given the PLIC source number, return the number of the GPIO pin associated
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* with the interrupt
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*/
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static inline int gpio_sifive_plic_to_pin(unsigned int base_irq, int plic_irq)
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{
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unsigned int level = _irq_level(base_irq);
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if (level == 2) {
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base_irq = _level2_irq(base_irq);
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}
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return (plic_irq - base_irq);
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}
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static void gpio_sifive_irq_handler(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct gpio_sifive_data *data = DEV_GPIO_DATA(dev);
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
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/* Calculate pin and mask from base level 2 line */
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uint8_t pin = 1 + (riscv_plic_get_irq() - (uint8_t)(cfg->gpio_irq_base >> 8));
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/* This peripheral tracks each condition separately: a
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* transition from low to high will mark the pending bit for
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* both rise and high, while low will probably be set from the
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* previous state.
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*
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* It is certainly possible, especially on double-edge, that
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* multiple conditions are present. However, there is no way
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* to tell which one occurred first, and no provision to
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* indicate which one occurred in the callback.
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*
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* Clear all the conditions so we only invoke the callback
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* once. Level conditions will remain set after clear.
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*/
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gpio->rise_ip = BIT(pin);
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gpio->fall_ip = BIT(pin);
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gpio->high_ip = BIT(pin);
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gpio->low_ip = BIT(pin);
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/* Call the corresponding callback registered for the pin */
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gpio_fire_callbacks(&data->cb, dev, BIT(pin));
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}
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/**
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* @brief Configure pin
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*
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* @param dev Device structure
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_sifive_config(struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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if (pin >= SIFIVE_PINMUX_PINS) {
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return -EINVAL;
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}
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/* We cannot support open-source open-drain configuration */
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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/* We only support pull-ups, not pull-downs */
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if ((flags & GPIO_PULL_DOWN) != 0) {
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return -ENOTSUP;
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}
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/* Set pull-up if requested */
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WRITE_BIT(gpio->pue, pin, flags & GPIO_PULL_UP);
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/* Set the initial output value before enabling output to avoid
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* glitches
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*/
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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gpio->out_val |= BIT(pin);
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}
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if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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gpio->out_val &= ~BIT(pin);
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}
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/* Enable input/output */
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WRITE_BIT(gpio->out_en, pin, flags & GPIO_OUTPUT);
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WRITE_BIT(gpio->in_en, pin, flags & GPIO_INPUT);
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return 0;
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}
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static int gpio_sifive_port_get_raw(struct device *dev,
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gpio_port_value_t *value)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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*value = gpio->in_val;
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return 0;
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}
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static int gpio_sifive_port_set_masked_raw(struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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gpio->out_val = (gpio->out_val & ~mask) | (value & mask);
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return 0;
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}
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static int gpio_sifive_port_set_bits_raw(struct device *dev,
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gpio_port_pins_t mask)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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gpio->out_val |= mask;
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return 0;
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}
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static int gpio_sifive_port_clear_bits_raw(struct device *dev,
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gpio_port_pins_t mask)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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gpio->out_val &= ~mask;
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return 0;
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}
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static int gpio_sifive_port_toggle_bits(struct device *dev,
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gpio_port_pins_t mask)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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gpio->out_val ^= mask;
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return 0;
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}
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static int gpio_sifive_pin_interrupt_configure(struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
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gpio->rise_ie &= ~BIT(pin);
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gpio->fall_ie &= ~BIT(pin);
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gpio->high_ie &= ~BIT(pin);
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gpio->low_ie &= ~BIT(pin);
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switch (mode) {
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case GPIO_INT_MODE_DISABLED:
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irq_disable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));
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break;
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case GPIO_INT_MODE_LEVEL:
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/* Board supports both levels, but Zephyr does not. */
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if (trig == GPIO_INT_TRIG_HIGH) {
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gpio->high_ip = BIT(pin);
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gpio->high_ie |= BIT(pin);
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} else {
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__ASSERT_NO_MSG(trig == GPIO_INT_TRIG_LOW);
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gpio->low_ip = BIT(pin);
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gpio->low_ie |= BIT(pin);
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}
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irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));
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break;
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case GPIO_INT_MODE_EDGE:
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__ASSERT_NO_MSG(GPIO_INT_TRIG_BOTH ==
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(GPIO_INT_LOW_0 | GPIO_INT_HIGH_1));
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if ((trig & GPIO_INT_HIGH_1) != 0) {
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gpio->rise_ip = BIT(pin);
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gpio->rise_ie |= BIT(pin);
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}
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if ((trig & GPIO_INT_LOW_0) != 0) {
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gpio->fall_ip = BIT(pin);
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gpio->fall_ie |= BIT(pin);
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}
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irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));
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break;
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default:
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__ASSERT(false, "Invalid MODE %d passed to driver", mode);
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_sifive_manage_callback(struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_sifive_data *data = DEV_GPIO_DATA(dev);
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return gpio_manage_callback(&data->cb, callback, set);
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}
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static const struct gpio_driver_api gpio_sifive_driver = {
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.pin_configure = gpio_sifive_config,
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.port_get_raw = gpio_sifive_port_get_raw,
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.port_set_masked_raw = gpio_sifive_port_set_masked_raw,
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.port_set_bits_raw = gpio_sifive_port_set_bits_raw,
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.port_clear_bits_raw = gpio_sifive_port_clear_bits_raw,
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.port_toggle_bits = gpio_sifive_port_toggle_bits,
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.pin_interrupt_configure = gpio_sifive_pin_interrupt_configure,
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.manage_callback = gpio_sifive_manage_callback,
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};
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/**
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* @brief Initialize a GPIO controller
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*
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* Perform basic initialization of a GPIO controller
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*
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* @param dev GPIO device struct
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*
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* @return 0
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*/
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static int gpio_sifive_init(struct device *dev)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
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/* Ensure that all gpio registers are reset to 0 initially */
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gpio->in_en = 0U;
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gpio->out_en = 0U;
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gpio->pue = 0U;
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gpio->rise_ie = 0U;
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gpio->fall_ie = 0U;
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gpio->high_ie = 0U;
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gpio->low_ie = 0U;
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gpio->invert = 0U;
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/* Setup IRQ handler for each gpio pin */
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cfg->gpio_cfg_func();
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return 0;
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}
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static void gpio_sifive_cfg_0(void);
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static const struct gpio_sifive_config gpio_sifive_config0 = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0),
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},
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.gpio_base_addr = DT_INST_REG_ADDR(0),
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.gpio_irq_base = DT_INST_IRQN(0),
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.gpio_cfg_func = gpio_sifive_cfg_0,
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};
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static struct gpio_sifive_data gpio_sifive_data0;
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DEVICE_AND_API_INIT(gpio_sifive_0, DT_INST_LABEL(0),
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gpio_sifive_init,
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&gpio_sifive_data0, &gpio_sifive_config0,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sifive_driver);
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#define IRQ_INIT(n) \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, n, irq), \
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CONFIG_GPIO_SIFIVE_##n##_PRIORITY, \
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gpio_sifive_irq_handler, \
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DEVICE_GET(gpio_sifive_0), \
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0);
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static void gpio_sifive_cfg_0(void)
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{
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#if DT_INST_IRQ_HAS_IDX(0, 0)
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IRQ_INIT(0);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 1)
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IRQ_INIT(1);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 2)
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IRQ_INIT(2);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 3)
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IRQ_INIT(3);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 4)
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IRQ_INIT(4);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 5)
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IRQ_INIT(5);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 6)
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IRQ_INIT(6);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 7)
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IRQ_INIT(7);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 8)
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IRQ_INIT(8);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 9)
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IRQ_INIT(9);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 10)
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IRQ_INIT(10);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 11)
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IRQ_INIT(11);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 12)
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IRQ_INIT(12);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 13)
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IRQ_INIT(13);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 14)
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IRQ_INIT(14);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 15)
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IRQ_INIT(15);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 16)
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IRQ_INIT(16);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 17)
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IRQ_INIT(17);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 18)
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IRQ_INIT(18);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 19)
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IRQ_INIT(19);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 20)
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IRQ_INIT(20);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 21)
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IRQ_INIT(21);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 22)
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IRQ_INIT(22);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 23)
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IRQ_INIT(23);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 24)
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IRQ_INIT(24);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 25)
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IRQ_INIT(25);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 26)
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IRQ_INIT(26);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 27)
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IRQ_INIT(27);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 28)
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IRQ_INIT(28);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 29)
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IRQ_INIT(29);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 30)
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IRQ_INIT(30);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 31)
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IRQ_INIT(31);
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#endif
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}
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