233 lines
5.9 KiB
ArmAsm
233 lines
5.9 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Fault handlers for ARCv2
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*
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* Fault handlers for ARCv2 processors.
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*/
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#define _ASMLANGUAGE
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#include <toolchain.h>
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#include <sections.h>
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#include <arch/cpu.h>
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#include "swap_macros.h"
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GTEXT(_Fault)
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GTEXT(__reset)
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GTEXT(__memory_error)
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GTEXT(__instruction_error)
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GTEXT(__ev_machine_check)
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GTEXT(__ev_tlb_miss_i)
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GTEXT(__ev_tlb_miss_d)
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GTEXT(__ev_prot_v)
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GTEXT(__ev_privilege_v)
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GTEXT(__ev_swi)
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GTEXT(__ev_trap)
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GTEXT(__ev_extension)
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GTEXT(__ev_div_zero)
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GTEXT(__ev_dc_error)
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GTEXT(__ev_maligned)
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SECTION_VAR(BSS, saved_stack_pointer)
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.word 0
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#if CONFIG_RGF_NUM_BANKS == 1
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GDATA(_exception_stack)
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SECTION_VAR(NOINIT, _exception_stack)
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.space 512
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/* note: QUARK_SE_C1000_SS can't afford 512B */
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#else
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GDATA(_firq_stack)
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#endif
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#if CONFIG_NUM_IRQ_PRIO_LEVELS == 1
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#error "NUM_IRQ_PRIO_LEVELS==1 is not supported."
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/* The code below sets bit 1 in AUX_IRQ_ACT and thus requires
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* priority 0 and 1 at a minimum. Supporting only 1 priority
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* requires a change to this file but also changes to make
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* FIRQ optional.
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*/
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#endif
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/*
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* @brief Fault handler installed in the fault and reserved vectors
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*/
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SECTION_SUBSEC_FUNC(TEXT,__fault,__memory_error)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__instruction_error)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_machine_check)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_tlb_miss_i)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_tlb_miss_d)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_prot_v)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_privilege_v)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_swi)
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#ifndef CONFIG_IRQ_OFFLOAD
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
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#endif
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_extension)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_div_zero)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_dc_error)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
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/*
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* Before invoking exception handler, the kernel switches to an exception
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* stack, to save the faulting thread's registers.
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* The exception is fatal and all the kernel can do is just print
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* a diagnostic message and halt.
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*/
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#ifdef CONFIG_ARC_STACK_CHECKING
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push_s r2
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/* disable stack checking */
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lr r2, [_ARC_V2_STATUS32]
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bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
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kflag r2
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pop_s r2
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#endif
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st sp, [saved_stack_pointer]
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#if CONFIG_RGF_NUM_BANKS == 1
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mov_s sp, _exception_stack
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add sp, sp, 512
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#else
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mov_s sp, _firq_stack
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add sp, sp, CONFIG_FIRQ_STACK_SIZE
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#endif
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/* save caller saved registers */
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_create_irq_stack_frame
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lr r0,[_ARC_V2_ERSTATUS]
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st_s r0, [sp, __tISF_status32_OFFSET]
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lr r0,[_ARC_V2_ERET]
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st_s r0, [sp, __tISF_pc_OFFSET] /* eret into pc */
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jl _Fault
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/* if _Fault returns, restore the registers */
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_pop_irq_stack_frame
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/* now restore the stack */
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ld sp,[saved_stack_pointer]
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rtie
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#ifdef CONFIG_IRQ_OFFLOAD
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GTEXT(_irq_do_offload);
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
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/*
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* Before invoking exception handler, the kernel switches to an exception
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* stack to save the faulting thread's registers.
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* The exception is fatal and all the kernel can do is just print
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* a diagnostic message and halt.
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*/
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#ifdef CONFIG_ARC_STACK_CHECKING
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push_s r2
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/* disable stack checking */
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lr r2, [_ARC_V2_STATUS32]
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bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
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kflag r2
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pop_s r2
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#endif
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/* save caller saved registers */
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_create_irq_stack_frame
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lr r0,[_ARC_V2_ERSTATUS]
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st_s r0, [sp, __tISF_status32_OFFSET]
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lr r0,[_ARC_V2_ERET]
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st_s r0, [sp, __tISF_pc_OFFSET] /* eret into pc */
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jl _irq_do_offload
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mov_s r1, _nanokernel
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ld_s r2, [r1, __tNANO_current_OFFSET]
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#if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
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/* check if we're a nested interrupt: if so, let the
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* interrupted interrupt handle the reschedule
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*/
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lr r3, [_ARC_V2_AUX_IRQ_ACT]
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/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
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* AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is 0, it
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* means trap was taken from outside an interrupt handler.
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* But if it was inside, let that handler do the swap.
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*/
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breq r3, 0, _trap_check_for_swap
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_trap_return:
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_pop_irq_stack_frame
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rtie
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#endif
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.balign 4
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_trap_check_for_swap:
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/* coop thread ? do not schedule */
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ld_s r0, [r2, __tTCS_prio_OFFSET]
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brlt r0, 0, _trap_return
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/* scheduler locked ? do not schedule */
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ld_s r0, [r2, __tTCS_sched_locked_OFFSET]
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brgt r0, 0, _trap_return
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/* check if the current thread needs to be rescheduled */
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push_s r2
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push_s r1
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push_s blink
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jl _is_next_thread_current
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pop_s blink
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pop_s r1
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pop_s r2
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brne r0, 0, _trap_return
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_save_callee_saved_regs
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st _CAUSE_RIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
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/* note: Ok to use _CAUSE_RIRQ since everything is saved */
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/*
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* Save needed registers to callee saved ones. It is faster than
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* pushing registers to stack. It is possible to do since program has
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* just saved them and the calling routine will save them in turn
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* if it uses them.
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*/
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mov_s r13, blink
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mov_s r14, r0
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mov_s r15, r1
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jl _get_next_ready_thread
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mov_s r2, r0
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mov_s r1, r15
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mov_s r0, r14
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mov_s blink, r13
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st_s r2, [r1, __tNANO_current_OFFSET]
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/* clear AE bit to forget this was an exception */
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lr r3, [_ARC_V2_STATUS32]
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and r3,r3,(~_ARC_V2_STATUS32_AE)
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kflag r3
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/* pretend lowest priority interrupt happened to use common handler */
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lr r3, [_ARC_V2_AUX_IRQ_ACT]
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or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
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sr r3, [_ARC_V2_AUX_IRQ_ACT]
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/* Assumption: r2 has current thread */
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b _rirq_common_interrupt_swap
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#endif /* CONFIG_IRQ_OFFLOAD */
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