zephyr/soc
Peter A. Bigot c76dd1edb7 soc: arm: nordic_nrf: change default SYS_CLOCKS_PER_SEC
The default system clock on all Nordic devices is based on a 32 KiHz
(2^15 Hz) timer.  Scheduling ticks requires that deadlines be specified
with a timer counter that aligns to a system clock.  With the Zephyr
default 100 clocks-per-sec configuration this results in 100 ticks every
32700 ticks of the cycle timer.  This reveals two problems:

* The uptime clock misrepresents elapsed time because it runs 0.208%
  (68/32768) faster than the best available clock;

* Calculation of timer counter compare values often requires an integer
  division and multiply operation to produce a value that's a multiple
  of clock-ticks-per-second.

Integer division on the Cortex-M1 nRF51 is done in software with a
(value-dependent) algorithm with a non-constant runtime that can be
significant.  This can produce missed Bluetooth deadlines as discussed
in upstream #14577 and others.

By changing the default divisor to one that evenly divides the 2^15
clock rate the time interrupts are disabled to manage timers is
significantly reduced, as is the error between uptime and real time.  Do
this at the top level, moving SYS_CLOCK_HW_CYCLES_PER_SEC there as well
since the two parameters are related.

Note that the central_hr configuration described in upstream #13610 does
not distinguish latency due to timer management from other
irq_block/spinlock regions, and the maximum observed latency will still
exceed the nominal 10 us allowed maximum.  However this does occur
much less frequently than changing the timer deadline which can happen
multiple times per tick.

Signed-off-by: Peter A. Bigot <pab@pabigot.com>
2019-05-07 14:32:21 +02:00
..
arc boards: iotdk: add mpu and fpu configuration 2019-04-29 09:03:24 -07:00
arm soc: arm: nordic_nrf: change default SYS_CLOCKS_PER_SEC 2019-05-07 14:32:21 +02:00
nios2 uart/ns16550, drivers/pcie: add PCI(e) support 2019-04-17 10:50:05 -07:00
posix license: cleanup: add SPDX Apache-2.0 license identifier 2019-04-07 08:45:22 -04:00
riscv32 soc: riscv32: Move rv32m1 flash memory definitions to dts 2019-05-06 19:09:59 -04:00
x86 boards/x86/up_squared: move UART configuration to apollo_lake.dtsi 2019-05-04 18:29:32 -04:00
x86_64/x86_64 license: cleanup: add SPDX Apache-2.0 license identifier 2019-04-07 08:45:22 -04:00
xtensa soc: intel_s1000: change cached regions to write-through 2019-04-12 17:59:06 -04:00
Kconfig license: cleanup: add SPDX Apache-2.0 license identifier 2019-04-07 08:45:22 -04:00