zephyr/soc/riscv32/riscv-privilege/common
Anas Nashif c2c6a6a245 qemu_riscv32: use hifive1 configuration
Use hifive1 configuration for this qemu and set
SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000

Fixes #10043

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-11-05 11:00:38 -05:00
..
CMakeLists.txt
idle.c
soc_common.h
soc_common_irq.c
soc_irq.S
vector.S