81 lines
1.5 KiB
Plaintext
81 lines
1.5 KiB
Plaintext
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <dt-bindings/clock/nxp_s32k146_clock.h>
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#include <nxp/nxp_s32k1xx.dtsi>
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/ {
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cpus {
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cpu@0 {
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compatible = "arm,cortex-m4f";
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};
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};
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soc {
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/*
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* SRAM_L and SRAM_U ranges form a contiguous block but misaligned
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* and burst accesses cannot occur across the 0x20000000 boundary
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* that separates the two SRAM arrays. Hence, treat the two arrays
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* as separate memory ranges.
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*/
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sram_l: sram@1fff0000 {
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compatible = "mmio-sram";
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reg = <0x1fff0000 DT_SIZE_K(64)>;
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};
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sram_u: sram@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(60)>;
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};
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};
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};
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/delete-node/ &lpi2c1;
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/delete-node/ &ftm6;
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/delete-node/ &ftm7;
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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&ftfc {
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 DT_SIZE_M(1)>;
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erase-block-size = <DT_SIZE_K(4)>;
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write-block-size = <8>;
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};
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};
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&lpuart2 {
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clocks = <&clock NXP_S32_LPUART2_CLK>;
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};
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&lpspi1 {
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clocks = <&clock NXP_S32_LPSPI1_CLK>;
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};
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&lpspi2 {
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clocks = <&clock NXP_S32_LPSPI2_CLK>;
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};
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&flexcan0 {
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interrupts = <78 0>, <79 0>, <80 0>, <81 0>, <82 0>;
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interrupt-names = "warning", "error", "wake-up", "mb-0-15", "mb-16-31";
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};
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&flexcan1 {
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interrupts = <85 0>, <86 0>, <88 0>, <89 0>;
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interrupt-names = "warning", "error", "mb-0-15", "mb-16-31";
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clocks = <&clock NXP_S32_FLEXCAN1_CLK>;
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};
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&flexcan2 {
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interrupts = <92 0>, <93 0>, <95 0>;
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interrupt-names = "warning", "error", "mb-0-15";
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clocks = <&clock NXP_S32_FLEXCAN2_CLK>;
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};
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