383 lines
7.8 KiB
Plaintext
383 lines
7.8 KiB
Plaintext
/*
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* Copyright 2023-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/clock/scg_k4.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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/ {
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aliases {
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watchdog0 = &wdog0;
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};
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chosen {
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zephyr,bt-hci = &hci;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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ctcm: sram@14000000 {
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ranges = <0x0 0x14000000 DT_SIZE_K(16)>;
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#address-cells = <1>;
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#size-cells = <1>;
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ctcm0: code_memory@0 {
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compatible = "mmio-sram";
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reg = <0x0 DT_SIZE_K(16)>;
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};
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};
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stcm: sram@30000000 {
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ranges = <0x0 0x30000000 DT_SIZE_K(112)>;
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#address-cells = <1>;
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#size-cells = <1>;
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stcm0: system_memory@0 {
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compatible = "mmio-sram";
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/* With only the first 64KB having ECC */
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reg = <0x0 DT_SIZE_K(104)>;
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};
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stcm1: system_memory@1a000 {
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compatible = "zephyr,memory-region","mmio-sram";
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reg = <0x1a000 DT_SIZE_K(8)>;
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zephyr,memory-region = "RetainedMem";
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};
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};
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smu2: sram@489c0000 {
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ranges = <0x0 0x489c0000 DT_SIZE_K(40)>;
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};
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peripheral: peripheral@50000000 {
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ranges = <0x0 0x50000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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pbridge2: pbridge2@0 {
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ranges = <>;
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reg = <0x0 0x4b000>;
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#address-cells = <1>;
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#size-cells = <1>;
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fmu: memory-controller@20000 {
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ranges = <0x0 0x10000000 DT_SIZE_M(1)>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "nxp,msf1";
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reg = <0x20000 0x1000>;
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interrupts = <27 0>;
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status = "disabled";
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flash: flash@0 {
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reg = <0x0 DT_SIZE_M(1)>;
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compatible = "soc-nv-flash";
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write-block-size = <16>;
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erase-block-size = <8192>;
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};
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};
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};
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fast_peripheral0: fast_peripherals0@8000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x8000000 0x40000>;
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};
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fast_peripheral1: fast_peripherals1@8800000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x8800000 0x210000>;
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};
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};
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};
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pinctrl: pinctrl {
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compatible = "nxp,kinetis-pinctrl";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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&smu2 {
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#address-cells = <1>;
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#size-cells = <1>;
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rpmsgmem: memory@8800 {
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compatible = "zephyr,memory-region","mmio-sram";
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reg = <0x8800 DT_SIZE_K(6)>;
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zephyr,memory-region = "rpmsg_sh_mem";
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zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
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};
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};
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&pbridge2 {
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#address-cells = <1>;
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#size-cells = <1>;
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scg: clock-controller@1e000 {
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compatible = "nxp,scg-k4";
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reg = <0x1e000 0x404>;
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#clock-cells = <2>;
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};
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porta: pinctrl@42000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x42000 0xe0>;
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clocks = <&scg SCG_K4_SLOW_CLK 0x108>;
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};
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portb: pinctrl@43000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x43000 0xe0>;
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clocks = <&scg SCG_K4_SLOW_CLK 0x10c>;
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};
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portc: pinctrl@44000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x44000 0xe0>;
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clocks = <&scg SCG_K4_SLOW_CLK 0x110>;
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};
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portd: pinctrl@45000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x45000 0xe0>;
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clocks = <&scg SCG_K4_SLOW_CLK 0>;
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};
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lpuart0: serial@38000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x38000 0x34>;
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interrupts = <44 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
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status = "disabled";
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};
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lpuart1: serial@39000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x39000 0x34>;
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interrupts = <45 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
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status = "disabled";
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};
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lpi2c0: i2c@33000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x33000 0x200>;
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interrupts = <39 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
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status = "disabled";
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};
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lpi2c1: i2c@34000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x34000 0x200>;
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interrupts = <40 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
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status = "disabled";
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};
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lpspi0: spi@36000 {
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compatible = "nxp,imx-lpspi";
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reg = <0x36000 0x800>;
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interrupts = <42 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0xd8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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lpspi1: spi@37000 {
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compatible = "nxp,imx-lpspi";
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reg = <0x37000 0x800>;
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interrupts = <43 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0xdc>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gpiod: gpio@46000{
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portd>;
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reg = <0x46000 0x128>;
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interrupts = <65 0>, <66 0>;
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};
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vbat: vbat@2b000 {
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reg = <0x2b000 0x400>;
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interrupts = <74 0>;
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};
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tpm0: pwm@31000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x31000 0x100>;
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interrupts = <37 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0xc4>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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tpm1: pwm@32000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x32000 0x100>;
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interrupts = <38 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0xc8>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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wdog0: watchdog@1a000 {
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compatible = "nxp,kinetis-wdog32";
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reg = <0x1a000 16>;
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interrupts = <23 0>;
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clocks = <&scg SCG_K4_SYSOSC_CLK 0x68>;
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clk-source = <1>;
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clk-divider = <256>;
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status = "okay";
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};
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wdog1: watchdog@1b000 {
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compatible = "nxp,kinetis-wdog32";
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reg = <0x1b000 16>;
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interrupts = <24 0>;
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clocks = <&scg SCG_K4_SYSOSC_CLK 0x6c>;
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clk-source = <1>;
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clk-divider = <256>;
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status = "disabled";
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};
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lptmr0: timer@2d000 {
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compatible = "nxp,lptmr";
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reg = <0x2d000 0x10>;
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interrupts = <34 0>;
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clock-frequency = <32000>;
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clk-source = <2>;
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prescaler = <1>;
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resolution = <32>;
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status = "disabled";
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};
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lptmr1: timer@2e000 {
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compatible = "nxp,lptmr";
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reg = <0x2e000 0x10>;
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interrupts = <35 0>;
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clock-frequency = <32000>;
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clk-source = <2>;
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prescaler = <1>;
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resolution = <32>;
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status = "disabled";
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};
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hci: hci_ble {
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compatible = "nxp,hci-ble";
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interrupts = <48 2>;
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interrupt-names = "hci_int";
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};
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flexcan0: can@3b000 {
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compatible = "nxp,flexcan";
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reg = <0x3b000 0x3080>;
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interrupts = <47 0>;
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interrupt-names = "common";
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clocks = <&scg SCG_K4_FIRC_CLK 0xec>;
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clk-source = <2>;
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status = "disabled";
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};
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adc0: adc@47000 {
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compatible = "nxp,lpc-lpadc";
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reg = <0x47000 0x1000>;
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interrupts = <71 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0x11c>;
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voltage-ref= <1>;
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calibration-average = <128>;
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/* pwrlvl 0 is slow speed low power, 1 is opposite */
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power-level = <0>;
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offset-value-a = <0>;
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offset-value-b = <0>;
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#io-channel-cells = <1>;
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nxp,references = <&vref 1800>;
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status = "disabled";
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};
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vref: regulator@4a000 {
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compatible = "nxp,vref";
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regulator-name = "mcxw71-vref";
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reg = <0x4a000 0x20>;
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#nxp,reference-cells = <1>;
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nxp,buffer-startup-delay-us = <400>;
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nxp,bandgap-startup-time-us = <20>;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <2100000>;
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nxp,current-compensation-en;
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status = "disabled";
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};
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};
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&fast_peripheral0 {
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gpioa: gpio@10000{
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porta>;
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reg = <0x10000 0x128>;
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interrupts = <59 0>, <60 0>;
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};
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gpiob: gpio@20000{
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portb>;
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reg = <0x20000 0x128>;
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interrupts = <61 0>, <62 0>;
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};
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gpioc: gpio@30000{
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portc>;
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reg = <0x30000 0x128>;
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interrupts = <63 0>, <64 0>;
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};
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};
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