320 lines
7.1 KiB
Plaintext
320 lines
7.1 KiB
Plaintext
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/imx95_clock.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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scmi_shmem0: memory@44611000 {
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compatible = "arm,scmi-shmem";
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reg = <0x44611000 0x80>;
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};
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};
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firmware {
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scmi {
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compatible = "arm,scmi";
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shmem = <&scmi_shmem0>;
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mboxes = <&mu5 0>;
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mbox-names = "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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compatible = "arm,scmi-clock";
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_iomuxc: protocol@19 {
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compatible = "arm,scmi-pinctrl";
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reg = <0x19>;
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pinctrl: pinctrl {
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compatible = "nxp,imx95-pinctrl", "nxp,imx93-pinctrl";
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};
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};
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};
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};
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soc {
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itcm: itcm@0 {
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compatible = "nxp,imx-itcm";
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reg = <0x0 DT_SIZE_K(256)>;
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};
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dtcm: dtcm@20000000 {
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compatible = "nxp,imx-dtcm";
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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edma2: dma@42000000 {
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compatible = "nxp,edma";
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reg = <0x42000000 (DT_SIZE_K(64) * 33)>;
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valid-channels = <30>, <31>;
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interrupts = <143 0>, <143 0>;
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#dma-cells = <2>;
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status = "disabled";
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};
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tpm3: pwm@424e0000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x424e0000 0x88>;
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interrupts = <73 0>;
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clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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tpm4: pwm@424f0000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x424f0000 0x88>;
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interrupts = <74 0>;
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clocks = <&scmi_clk IMX95_CLK_TPM4>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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tpm5: pwm@42500000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x42500000 0x88>;
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interrupts = <75 0>;
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clocks = <&scmi_clk IMX95_CLK_TPM5>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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tpm6: pwm@42510000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x42510000 0x88>;
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interrupts = <76 0>;
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clocks = <&scmi_clk IMX95_CLK_TPM6>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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lpi2c3: i2c@42530000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x42530000 0x4000>;
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interrupts = <58 0>;
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clocks = <&scmi_clk IMX95_CLK_LPI2C3>;
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status = "disabled";
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};
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lpi2c4: i2c@42540000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x42540000 0x4000>;
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interrupts = <59 0>;
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clocks = <&scmi_clk IMX95_CLK_LPI2C4>;
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status = "disabled";
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};
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lpuart3: serial@42570000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x42570000 DT_SIZE_K(64)>;
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interrupts = <64 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART3>;
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status = "disabled";
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};
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lpuart4: serial@42580000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x42580000 DT_SIZE_K(64)>;
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interrupts = <65 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART4>;
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status = "disabled";
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};
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lpuart5: serial@42590000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x42590000 DT_SIZE_K(64)>;
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interrupts = <66 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART5>;
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status = "disabled";
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};
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lpuart6: serial@425a0000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x425a0000 DT_SIZE_K(64)>;
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interrupts = <67 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART6>;
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status = "disabled";
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};
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sai3: dai@42650000 {
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compatible = "nxp,dai-sai";
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reg = <0x42650000 DT_SIZE_K(64)>;
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clocks = <&scmi_clk IMX95_CLK_SAI3>;
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clock-names = "mclk1";
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interrupts = <170 0>;
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dai-index = <3>;
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mclk-is-output;
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dmas = <&edma2 30 60>, <&edma2 31 61>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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lpuart7: serial@42690000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x42690000 DT_SIZE_K(64)>;
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interrupts = <68 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART7>;
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status = "disabled";
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};
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lpuart8: serial@426a0000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x426a0000 DT_SIZE_K(64)>;
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interrupts = <69 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART8>;
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status = "disabled";
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};
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lpi2c5: i2c@426b0000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x426b0000 0x4000>;
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interrupts = <181 0>;
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clocks = <&scmi_clk IMX95_CLK_LPI2C5>;
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status = "disabled";
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};
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lpi2c6: i2c@426c0000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x426c0000 0x4000>;
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interrupts = <182 0>;
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clocks = <&scmi_clk IMX95_CLK_LPI2C6>;
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status = "disabled";
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};
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lpi2c7: i2c@426d0000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x426d0000 0x4000>;
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interrupts = <183 0>;
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clocks = <&scmi_clk IMX95_CLK_LPI2C7>;
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status = "disabled";
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};
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lpi2c8: i2c@426e0000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x426e0000 0x4000>;
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interrupts = <184 0>;
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clocks = <&scmi_clk IMX95_CLK_LPI2C8>;
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status = "disabled";
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};
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tpm1: pwm@44310000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x44310000 0x88>;
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interrupts = <29 0>;
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clocks = <&scmi_clk IMX95_CLK_BUSAON>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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tpm2: pwm@44320000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x44320000 0x88>;
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interrupts = <30 0>;
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clocks = <&scmi_clk IMX95_CLK_TPM2>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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lpi2c1: i2c@44340000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44340000 0x4000>;
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interrupts = <13 0>;
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clocks = <&scmi_clk IMX95_CLK_LPI2C1>;
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status = "disabled";
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};
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lpi2c2: i2c@44350000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44350000 0x4000>;
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interrupts = <14 0>;
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clocks = <&scmi_clk IMX95_CLK_LPI2C2>;
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status = "disabled";
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};
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lpuart1: serial@44380000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x44380000 DT_SIZE_K(64)>;
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interrupts = <19 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART1>;
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status = "disabled";
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};
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lpuart2: serial@44390000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x44390000 DT_SIZE_K(64)>;
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interrupts = <20 3>;
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clocks = <&scmi_clk IMX95_CLK_LPUART2>;
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status = "disabled";
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};
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mu5: mailbox@44610000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x44610000 DT_SIZE_K(4)>;
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interrupts = <205 0>;
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#mbox-cells = <1>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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