72 lines
2.0 KiB
Plaintext
72 lines
2.0 KiB
Plaintext
/*
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* Copyright (c) 2022 Telink Semiconductor
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pinctrl/b91-pinctrl.h>
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&pinctrl {
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/* Set pad-mul-sel register value.
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* Note: Pins functions below (pinmux = <...>) depend on this value.
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*/
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pad-mul-sel = <1>;
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/* UART0: TX(PB2), RX(PB3) */
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uart0_tx_pb2_default: uart0_tx_pb2_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_B, B91_PIN_2, B91_FUNC_C)>;
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};
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uart0_rx_pb3_default: uart0_rx_pb3_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_B, B91_PIN_3, B91_FUNC_C)>;
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};
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/* UART1: TX(PC6), RX(PC7) */
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uart1_tx_pc6_default: uart1_tx_pc6_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_C, B91_PIN_6, B91_FUNC_C)>;
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};
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uart1_rx_pc7_default: uart1_rx_pc7_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_C, B91_PIN_7, B91_FUNC_C)>;
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};
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/* PWM Channel 0 (PB4) */
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pwm_ch0_pb4_default: pwm_ch0_pb4_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_B, B91_PIN_4, B91_FUNC_B)>;
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};
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/* PSPI: CLK(PC5), MOSI(PC7), MISO(PC6) */
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pspi_clk_pc5_default: pspi_clk_pc5_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_C, B91_PIN_5, B91_FUNC_A)>;
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};
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pspi_mosi_pc7_default: pspi_mosi_pc7_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_C, B91_PIN_7, B91_FUNC_A)>;
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};
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pspi_miso_pc6_default: pspi_miso_pc6_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_C, B91_PIN_6, B91_FUNC_A)>;
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};
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/* HSPI: CLK(PA2), MOSI(PA4), MISO(PA3) */
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hspi_clk_pa2_default: hspi_clk_pa2_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_A, B91_PIN_2, B91_FUNC_C)>;
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};
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hspi_mosi_pa4_default: hspi_mosi_pa4_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_A, B91_PIN_4, B91_FUNC_C)>;
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};
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hspi_miso_pa3_default: hspi_miso_pa3_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_A, B91_PIN_3, B91_FUNC_C)>;
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};
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/* Define I2C pins: SCL(PE1), SDA(PE3) */
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i2c_scl_pe1_default: i2c_scl_pe1_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_E, B91_PIN_1, B91_FUNC_A)>;
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};
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i2c_sda_pe3_default: i2c_sda_pe3_default {
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pinmux = <B91_PINMUX_SET(B91_PORT_E, B91_PIN_3, B91_FUNC_A)>;
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};
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};
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