104 lines
2.9 KiB
ArmAsm
104 lines
2.9 KiB
ArmAsm
/* isr_wrapper.S - ARM CORTEX-M3 wrapper for ISRs with parameter */
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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DESCRIPTION
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Wrapper installed in vector table for handling dynamic interrupts that accept
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a parameter.
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*/
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#define _ASMLANGUAGE
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#include <offsets.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <sw_isr_table.h>
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#include <nano_private.h>
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#include <arch/cpu.h>
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_ASM_FILE_PROLOGUE
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GDATA(_sw_isr_table)
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GTEXT(_isr_wrapper)
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GTEXT(_IntExit)
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/**
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*
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* @brief Wrapper around ISRs when inserted in software ISR table
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*
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* When inserted in the vector table, _isr_wrapper() demuxes the ISR table using
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* the running interrupt number as the index, and invokes the registered ISR
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* with its correspoding argument. When returning from the ISR, it determines
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* if a context switch needs to happen (see documentation for __pendsv()) and
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* pends the PendSV exception if so: the latter will perform the context switch
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* itself.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _isr_wrapper)
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_GDB_STUB_EXC_ENTRY
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push {lr} /* lr is now the first item on the stack */
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT
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push {lr}
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bl _sys_k_event_logger_interrupt
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pop {lr}
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#endif
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#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
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/*
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* All interrupts are disabled when handling idle wakeup. For tickless
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* idle, this ensures that the calculation and programming of the device
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* for the next timer deadline is not interrupted. For non-tickless idle,
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* this ensures that the clearing of the kernel idle state is not
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* interrupted. In each case, _sys_power_save_idle_exit is called with
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* interrupts disabled.
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*/
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cpsid i /* PRIMASK = 1 */
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/* is this a wakeup from idle ? */
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ldr r2, =_nanokernel
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ldr r0, [r2, #__tNANO_idle_OFFSET] /* requested idle duration, in ticks */
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cmp r0, #0
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ittt ne
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movne r1, #0
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strne r1, [r2, #__tNANO_idle_OFFSET] /* clear kernel idle state */
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blxne _sys_power_save_idle_exit
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cpsie i /* re-enable interrupts (PRIMASK = 0) */
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#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
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mrs r0, IPSR /* get exception number */
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sub r0, r0, #16 /* get IRQ number */
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lsl r0, r0, #3 /* table is 8-byte wide */
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ldr r1, =_sw_isr_table
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add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
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* in thumb mode */
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ldmia r1,{r0,r3} /* arg in r0, ISR in r3 */
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blx r3 /* call ISR */
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pop {lr}
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/* exception return is done in _IntExit(), including _GDB_STUB_EXC_EXIT */
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b _IntExit
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