149 lines
4.3 KiB
ArmAsm
149 lines
4.3 KiB
ArmAsm
/* gdb_stub.S - extra work performed upon exception entry/exit for GDB */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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DESCRIPTION
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Prep work done when entering exceptions consists of saving the callee-saved
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registers before they get used by exception handlers, and recording the fact
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that we are running in an exception.
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Upon exception exit, it must be recorded that the task is not in an exception
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anymore.
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*/
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#define _ASMLANGUAGE
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#include <offsets.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <nano_private.h>
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#include <arch/cpu.h>
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_ASM_FILE_PROLOGUE
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/**
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*
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* @brief Exception entry extra work when GDB_INFO is enabled
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*
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* During normal system operation, the callee-saved registers are saved lazily
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* only when a context switch is required. To allow looking at the current
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* threads registers while debugging an exception/interrupt, they must be saved
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* upon entry since the handler could be using them: thus, looking at the CPU
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* registers would show the current system state and not the current *thread*'s
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* state.
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*
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* Also, record the fact that the thread is currently interrupted so that VQEMU
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* looks into the TCS and not the CPU registers to obtain the current thread's
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* register values.
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*
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* NOTE:
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* - must be called with interrupts locked
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* - cannot use r0 without saving it first
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _GdbStubExcEntry)
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ldr r1, =_nanokernel
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ldr r2, [r1, #__tNANO_flags_OFFSET]
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/* already in an exception, do not update the registers */
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ands r3, r2, #EXC_ACTIVE
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it ne
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bxne lr
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orrs r2, #EXC_ACTIVE
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str r2, [r1, #__tNANO_flags_OFFSET]
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ldr r1, [r1, #__tNANO_current_OFFSET]
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str r2, [r1, #__tTCS_flags_OFFSET]
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/* save callee-saved + psp in TCS */
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adds r1, #__tTCS_preempReg_OFFSET
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mrs ip, PSP
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stmia r1, {v1-v8, ip}
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bx lr
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/**
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*
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* @brief Exception exit extra clean up when GDB_INFO is enabled
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*
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* Record the fact that the thread is not interrupted anymore so that VQEMU
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* looks at the CPU registers and not into the TCS to obtain the current
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* thread's register values. Only do this if this is not a nested exception.
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*
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* NOTE:
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* - must be called with interrupts locked
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* - cannot use r0 without saving it first
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _GdbStubExcExit)
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/* if we're nested (ie. !RETTOBASE), do not reset EXC_ACTIVE */
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ldr r1, =_SCS_ICSR
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ldr r1, [r1]
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ands r1, #_SCS_ICSR_RETTOBASE
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it eq
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bxeq lr
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ldr r1, =_nanokernel
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ldr r2, [r1, #__tNANO_flags_OFFSET]
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bic r2, #EXC_ACTIVE
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str r2, [r1, #__tNANO_flags_OFFSET]
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ldr r1, [r1, #__tNANO_current_OFFSET]
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str r2, [r1, #__tTCS_flags_OFFSET]
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bx lr
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/**
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*
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* @brief Stub for ISRs installed directly in vector table
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*
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* The kernel on Cortex-M3/4 can be configured so that ISRs
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* are installed directly in the vector table for maximum efficiency.
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*
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* When OS-awareness is enabled, a stub must be inserted to invoke
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* _GdbStubExcEntry() before the user ISR runs, to save the current task's
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* registers. This stub thus gets inserted in the vector table instead of the
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* user's ISR. The user's IRQ vector table gets pushed after the vector table
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* automatically by the linker script: this is all transparent to the user.
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* This stub must also act as a demuxer that find the running exception and
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* invoke the user's real ISR.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _irq_vector_table_entry_with_gdb_stub)
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_GDB_STUB_EXC_ENTRY
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mrs r0, IPSR /* get exception number */
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sub r0, r0, #16 /* get IRQ number */
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ldr r1, =_irq_vector_table
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/* grab real ISR at address: r1 + (r0 << 2) (table is 4-byte wide) */
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ldr r1, [r1, r0, LSL #2]
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/* jump to ISR, no return: ISR is responsible for calling _IntExit */
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bx r1
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