96 lines
3.3 KiB
ArmAsm
96 lines
3.3 KiB
ArmAsm
/* basepri.s - ARM Cortex-M interrupt locking via BASEPRI */
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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Provide irq_lock() and irq_unlock() via the BASEPRI register. This
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allows locking up to a certain interrupt priority. VxMicro locks out priorities
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2 and lower (higher numbered priorities), in essence leaving priorities 0 and 1
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unlocked. This achieves two purposes:
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1. The service call exception is installed at priority 0, allowing it to be
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invoked with interrupts locked. This is needed since 'svc #0' is the
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implementation of _Swap(), which is invoked with interrupts locked in the
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common implementation of nanokernel objects.
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2. Zero Interrupt Latency (ZLI) is achievable via this by allowing certain
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interrupts to set their priority to 1, thus being allowed in when interrupts
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are locked for regular interrupts.
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*/
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#define _ASMLANGUAGE
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#include <toolchain.h>
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#include <sections.h>
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#include <nanokernel/cpu.h>
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_ASM_FILE_PROLOGUE
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GTEXT(irq_lock)
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GTEXT(irq_unlock)
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/*******************************************************************************
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*
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* irq_lock - lock interrupts
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*
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* Prevent exceptions of priority lower than to the two highest priorities from
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* interrupting the CPU.
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*
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* This function can be called recursively: it will return a key to return the
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* state of interrupt locking to the previous level.
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*
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* RETURNS: a key to return to the previous interrupt locking level
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*/
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SECTION_FUNC(TEXT,irq_lock)
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movs.n r1, #_EXC_IRQ_DEFAULT_PRIO
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mrs r0, BASEPRI
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msr BASEPRI, r1
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bx lr
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/*******************************************************************************
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*
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* irq_unlock - unlock interrupts
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*
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* Return the state of interrupt locking to a previous level, passed in via the
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* <key> parameter, obtained from a previous call to irq_lock().
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*
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* RETURNS: N/A
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*/
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SECTION_FUNC(TEXT,irq_unlock)
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msr BASEPRI, r0
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bx lr
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.end
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