Daniel Leung 1e7025c2e7 boards: intel_s1000_crb: fix setting cache attributes ... This reverts commit c9ace83c89 which bypasses setting cache attributes. The previous cache attributes actually set the text/data/etc. sections to be inaccessible. So fix it. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2019-02-15 16:21:50 -05:00
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D_108mini	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
D_212GP	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
D_233L	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
XRC_D2PM_5swIrq	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
XRC_FUSION_AON_ALL_LM	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
esp32	dts: xtensa: esp32: Add device tree support.	2019-01-29 09:47:17 -06:00
hifi2_std	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
hifi3_bd5	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
hifi3_bd5_call0	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
hifi4_bd7	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
hifi_mini	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
hifi_mini_4swIrq	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
intel_s1000	boards: intel_s1000_crb: fix setting cache attributes	2019-02-15 16:21:50 -05:00
sample_controller	dts: qemu_xtensa/xt-sim: Enable device tree support	2019-02-01 07:49:28 -06:00