Daniel Leung 1e7025c2e7 boards: intel_s1000_crb: fix setting cache attributes ... This reverts commit c9ace83c89 which bypasses setting cache attributes. The previous cache attributes actually set the text/data/etc. sections to be inaccessible. So fix it. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2019-02-15 16:21:50 -05:00
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core	boards: intel_s1000_crb: fix setting cache attributes	2019-02-15 16:21:50 -05:00
include	arch: xtensa: Remove unused field from _thread_arch	2018-12-11 15:33:07 -05:00
CMakeLists.txt	xtensa: move soc to top-level dir soc/	2018-09-13 00:56:48 -04:00
Kconfig	Kconfig: Hide SMP and USE_SWITCH from unsupported platforms	2018-12-30 16:24:50 -05:00