Filip Kokosinski 00b2ef8744 dts: set the `riscv,isa` property for virt-based targets ... This commit makes the devicetrees of the targets that are based on the QEMU `virt` machine more consistent with the rest of the RISC-V targets in Zephyr by: * adding the `riscv,isa` property * adding a compatible string which uniquely identifies the `virt` core Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>		2024-05-15 09:30:23 +02:00
..
andes	dts: bindings: add andestech,l2c	2024-04-22 09:19:27 -04:00
efinix	dts/riscv/efinix: add the `efinix,vexriscv-sapphire` compatible string	2024-01-31 10:41:49 +01:00
espressif/esp32c3	dts: bindings: can: remove optional sample point properties	2024-03-17 15:36:19 +01:00
gd	dts/riscv: add `riscv` compatible string where it's missing	2024-01-31 10:41:49 +01:00
ite	ITE: soc: Add the variant of it81302dx	2024-05-13 11:39:10 +02:00
lowrisc	dts: opentitan: update plic interrupt count to match spec	2024-03-22 09:23:46 +00:00
microchip	dts: mbox: add PolarFire SoC mailbox interface	2024-02-01 04:33:16 -05:00
niosv	dts/riscv: add `riscv` compatible string where it's missing	2024-01-31 10:41:49 +01:00
nordic	dts: nordic: Change IRQ number for GPIOTE instances for nRF54L15	2024-04-25 12:43:58 +00:00
openisa	dts/riscv/openisa: add compatible strings for the RI5CY cores	2024-01-31 10:41:49 +01:00
qemu	dts: set the `riscv,isa` property for virt-based targets	2024-05-15 09:30:23 +02:00
sifive	dts: sifive: Update SoC compats	2024-04-18 14:56:00 +02:00
starfive	dts: jh7110: fix memory definitions	2024-04-09 14:20:39 +02:00
telink	drivers: intc: plic: define all registers' offset in the driver	2023-10-04 09:06:28 -04:00
neorv32.dtsi	dts/riscv: add `riscv` compatible string where it's missing	2024-01-31 10:41:49 +01:00
renode_riscv32_virt.dtsi	dts: riscv: add a SoC dtsi for Renode RISC-V Virt SoC	2024-01-08 12:35:10 +01:00
riscv32-litex-vexriscv.dtsi	dts/riscv/litex: add `litex,vexriscv-standard` compatible string	2024-01-31 10:41:49 +01:00